MC145572 Datasheet, PDF (45/264 Pages) Freescale Semiconductor, Inc – ISDN U-INTERFACE TRANSCEIVER

4.3.4
Freescale Semiconductor, Inc.
NR3: Interrupt Status Register
This is the interrupt status register, and it is read–only. All bits are cleared on Software Reset (NR0(b3))
or Hardware Reset (RESET). Each interrupt status bit in the register operates the same. If it is 1 and
its corresponding interrupt enable is 1 in Register NR4, the IRQ pin on the chip will become active.
IRQ3 has the highest priority and IRQ0 has the lowest.
NR3
b3
IRQ3
ro
b2
IRQ2
ro
b1
IRQ1
ro
b0
IRQ0
ro
IRQ3
This interrupt is set whenever there is a state change in NR1 and is cleared by reading NR1. If this
bit is set by the D channel register interrupt, it is cleared once OR12 has been read, unless there
has been a change in activation status.
IRQ2
This interrupt is dedicated to the eoc. Whenever the eoc buffer, Register R6, is updated by the Super-
frame Deframer, this bit is set. The loading of the eoc buffer is dependent on its mode of operation.
See Register BR9(b7:b6) for details of when the buffer is loaded. To clear the interrupt, it is necessary
to read Register R6, the eoc buffer register. IRQ2 is asserted at the end of the fourth and eighth basic
frame of a superframe.
IRQ1
This interrupt is dedicated to the received M4 maintenance bits. This bit is set whenever the M4 buffer,
Register BR1, is updated. The updating of the M4 buffer is dependent on its mode of operation. See
Register BR9(b5:b4) for details of when the buffer is updated. To clear the interrupt, it is necessary
to read Register BR1, which is the M4 receive buffer. IRQ1 is asserted at the end of every superframe.
IRQ0
This interrupt is dedicated to the received M50, M51, and M60 bits from basic frames 1 and 2 that
are buffered in Register BR3. Whenever these bits in Register BR3 are updated, this interrupt bit is
set. The updating of BR3 is dependent on its mode of operation. See Register BR9(b3:b2) for details
of when the buffer is updated. To clear the interrupt, it is necessary to read Register BR3. IRQ0 is
asserted at the end of the fourth received basic frame of a superframe.
4.3.5
NR4: Interrupt Mask Register
This is the interrupt mask register. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset
(RESET). Each bit operates in the the same manner. For example, if Enable IRQ1 is set to 1 by the
external microcontroller and the IRQ1 interrupt bit is set to 1 in NR3, the IRQ pin becomes active
when there is a change in activation status, or there is a D channel interrupt when D channel register
OR12 is updated.
NR4
b3
Enable IRQ3
rw
b2
Enable IRQ2
rw
b1
Enable IRQ1
rw
b0
Enable IRQ0
rw
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