MCIMX25_09 Datasheet, PDF (39/132 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

Table 26 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.
Table 26. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O
Parameter
Duty cycle
Clock frequency
Output pad transition times
Symbol
Fduty
f
tpr
Output pad propagation delay, 50%–50%
tpo
input signals and crossing of output signals
Output pad propagation delay, 40%–60%
tpo
input signals and crossing of output signals
Output enable to output valid delay,
tpv
50%–50%
Output enable to output valid delay,
tpv
40%–60%
Output pad slew rate
tps
Output pad dI/dt
tdit
Input pad transition times
trfi
Input pad propagation delay, 50%–50%
tpi
Input pad propagation delay, 40%–60%
tpi
Load
Condition
—
—
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
1.0 pF
1.0 pF
1.0 pF
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units Notes
40
50
60
%
—
—
—
133
MHz
—
0.53/0.52 0.80/0.72 1.19/1.04 ns
1
1.01/0.98 1.49/1.34 2.21/1.90
1.3/1.21 1.97/1.84 2.91/2.71 ns
1
1.59/1.5 2.37/2.24 3.48/3.28
1.47/1.38 2.13/2.00 3.072/2.87 ns
1
1.75/1.67 2.54/2.40 3.65/3.45
1.32/1.28 2.11/2.00 3.31/3.12 ns
1
1.66/1.65 2.61/2.50 4.06/3.81
1.40/1.37 2.16/2.06 3.30/3.13 ns
1
1.67/1.66 2.56/2.45 3.89/3.67
0.86/0.98 1.35/1.5 2.15/2.19 V/ns
2
0.46/054 0.72/0.81 1.12/1.16
72
172
400
mA/ns 3
77
183
422
0.07/0.08 0.10/0.12 0.17/0.20 ns
4
0.89/0.87 1.41/1.37 2.16/2.07 ns
1.71/1.69 2.22/2.18 2.98/2.88 ns
Note:
1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 27 shows the AC requirements for DDR2 I/O.
Table 27. AC Requirements for DDR2 I/O
Parameter¹
Symbol
Min.
Max.
Units
AC input logic high
VIH(ac)
OVDD/2 + 0.25
OVDD + 0.3
V
AC input logic low
AC differential input voltage²
AC differential cross point voltage for input³
AC differential cross point voltage for output⁴
VIL(ac)
–0.3
OVDD/2 – 0.25
V
Vid(ac)
0.5
OVDD + 0.6
V
Vix(ac)
OVDD/2–0.175
OVDD/2 + 0.175
V
Vox(ac)
OVDD/2–0.125
OVDD/2 + 0.125
V
1 _{Note that the Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any}
specification in this document.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2
Freescale Semiconductor
39