MCIMX25_09 Datasheet, PDF (104/132 Pages) Freescale Semiconductor, Inc – i.MX25 Applications Processor for Consumer and Industrial Products

3.6.17.2 SSI Receiver Timing with Internal Clock
Figure 79 shows the timing for the SSI receiver with internal clock. Table 78 describes the timing
parameters (SS1–SS51) shown in the figure.
SS1
SS5
SS3
SS2
SS4
AUDn_TXC
(Output)
SS7
AUDn_TXFS (bl)
(Output)
AUDn_TXFS (wl)
(Output)
AUDn_RXD
(Input)
SS48
SS9
SS11
SS20
SS47
SS51
SS50
SS21
SS49
SS13
AUDn_RXC
(Output)
Figure 79. SSI Receiver Internal Clock Timing Diagram
Table 78. SSI Receiver Timing with Internal Clock
ID
Parameter
Min.
Max.
Unit
SS1
SS2
SS3
SS4
SS5
SS7
SS9
SS11
SS13
SS20
SS21
SS47
Internal Clock Operation
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
Oversampling Clock Operation
Oversampling clock period
81.4
36.0
—
36.0
—
—
—
—
—
10.0
0.0
15.04
—
ns
—
ns
6.0
ns
—
ns
6.0
ns
15.0
ns
15.0
ns
15.0
ns
15.0
ns
—
ns
—
ns
—
ns
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2
104
Freescale Semiconductor