908E626_12 Datasheet, PDF (39/43 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
908E626
Introduction
This thermal addendum ia provided as a supplement to the MM908E626
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
54-PIN
SOICW-EP
Package and Thermal Considerations
This MM908E626 is a dual die package. There are two heat sources in the
package independently heating with P₁ and P₂. This results in two junction
temperatures, T_J1 and T_J2, and a thermal resistance matrix with R_JAmn.
For m, n = 1, R_JA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, R_JA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P₂. This applies to
R_J21 and R_J22, respectively.
98ARL10519D
54-PIN SOICW-EP
T_J1
T_J2
=
R_JA11
R_JA21
R_JA12
R_JA22
.
P₁
P₂
Note For package dimensions, refer to
98ARL10519D.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Table 12. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
R_JAmn ⁽¹⁾⁽²⁾
23
20
24
R_JBmn ⁽²⁾⁽³⁾
9.0
6.0
10
R_JAmn ⁽¹⁾⁽⁴⁾
52
47
52
R_JCmn ⁽⁵⁾
1.0
0
2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Thermal vias
connected to top
buried plane
Figure 20. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5Thermal Test Board
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E626
39