908E626_12 Datasheet, PDF (20/43 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
• 0 = High temperature condition has not occurred.
LVF — LOW VOLTAGE FLAG BIT
This read / write flag is set on a low voltage condition. Clear
LVF by writing a logic [1] to LVF. If a low voltage condition is
still present while writing a logic [1] to LVF, the writing has no
effect. Therefore, a low voltage interrupt cannot be lost due
to inadvertent clearing of LVF. Reset clears the LVF bit.
Writing a logic [0] to LVF has no effect.
• 1 = Low voltage condition has occurred.
• 0 = Low voltage condition has not occurred.
HVF — HIGH VOLTAGE FLAG BIT
This read / write flag is set on a high voltage condition.
Clear HVF by writing a logic [1] to HVF. If high voltage
condition is still present while writing a logic [1] to HVF, the
writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVF. Reset
clears the HVF bit. Writing a logic [0] to HVF has no effect.
• 1 = High voltage condition has occurred.
• 0 = High voltage condition has not occurred.
OCF — OVER-CURRENT FLAG BIT
This read-only flag is set on an over-current condition.
Reset clears the OCF bit. To clear this flag, write a logic [1] to
the appropriate over-current flag in the SYSSTAT Register.
See Figure 9, which shows the two signals triggering the
OCF.
• 1 = High current condition has occurred.
• 0 = High current condition has not occurred.
HVDD_OCF
HB_OCF
OCF
Figure 9. Principal Implementation for OCF
INTERRUPT MASK REGISTER (IMR)
Register Name and Address: IMR - $04
Bit7 6
5
4
3
2
1 Bit0
Read
0
Write
0
0 LINIE HTIE LVIE HVIE OCIE
Reset 0
0
0
0
0
0
0
0
LINIE — LIN LINE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
• 1 = Interrupt requests from LINF flag enabled.
• 0 = Interrupt requests from LINF flag disabled.
HTIE — HIGH TEMPERATURE INTERRUPT
ENABLE BIT
This read / write bit enables CPU interrupts by the high
temperature flag, HTF. Reset clears the HTIE bit.
• 1 = Interrupt requests from HTF flag enabled.
• 0 = Interrupt requests from HTF flag disabled.
LVIE — LOW VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the low
voltage flag, LVF. Reset clears the LVIE bit.
• 1 = Interrupt requests from LVF flag enabled.
• 0 = Interrupt requests from LVF flag disabled.
HVIE — HIGH VOLTAGE INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the high
voltage flag, HVF. Reset clears the HVIE bit.
• 1 = Interrupt requests from HVF flag enabled.
• 0 = Interrupt requests from HVF flag disabled.
OCIE — OVER-CURRENT INTERRUPT ENABLE BIT
This read / write bit enables CPU interrupts by the over-
current flag, OCF. Reset clears the OCIE bit.
• 1 = Interrupt requests from OCF flag enabled.
• 0 = Interrupt requests from OCF flag disabled.
RESET
The 908E626 chip has four internal reset sources and one
external reset source, as explained in the paragraphs below.
Figure 10 depicts the internal reset sources.
908E626
20
Analog Integrated Circuit Device Data
Freescale Semiconductor