56F8014_07 Datasheet, PDF (37/125 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Peripheral Memory Mapped Registers
Table 4-9 Interrupt Control Registers Address Map (Continued)
(ITCN_BASE = $00 F060)
Register Acronym Address Offset
Register Description
ITCN_FIM1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP 0
ITCN_IRQP 1
ITCN_IRQP 2
ITCN_ICTRL
$9
Fast Interrupt Match 1 Register
$A
Fast Interrupt Vector Address Low 1 Register
$B
Fast Interrupt Vector Address High 1 Register
$C
IRQ Pending Register 0
$D
IRQ Pending Register 1
$E
IRQ Pending Register 2
Reserved
$12
Interrupt Control Register
Reserved
Table 4-10 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym Address Offset
Register Description
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_SDIS
ADC_STAT
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_LOLIM0
ADC_LOLIM1
ADC_LOLIM2
ADC_LOLIM3
ADC_LOLIM4
ADC_LOLIM5
$0
Control Register 1
$1
Control Register 2
$2
Zero Crossing Control Register
$3
Channel List Register 1
$4
Channel List Register 2
$5
Sample Disable Register
$6
Status Register
$7
Limit Status Register
$8
Zero Crossing Status Register
$9
Result Register 0
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
Result Register 7
$11
Low Limit Register 0
$12
Low Limit Register 1
$13
Low Limit Register 2
$14
Low Limit Register 3
$15
Low Limit Register 4
$16
Low Limit Register 5
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
37
Preliminary