MC13883_10 Datasheet, PDF (34/64 Pages) Freescale Semiconductor, Inc – Integrated Charger USB Interface

Connectivity
The SW_DP2 switch is controlled by hardware. When the bus is idle, the switch is closed and the DP
pull-up resistor is set to 1.2 kΩ (900-1575 Ω), (SW_DP1 & SW_DP2 both closed). When the upstream
device is transmitting data (J-K transition or J-SE0 transition detected), the switch is open and the DP
pull-up resistor is set to about 2 kΩ (1425-3090 Ω), (SW_DP1 only closed).
In addition to the variable pull-up resistor, a 150 kΩ pull-up resistor to the VC supply is provided on the
DP (D+) line. This resistor is used for the accessory identification when the phone is on and the variable
pull-up is switched out. SW_DP3 connecting the 150 kΩ resistor is controlled by the DP_150K_PU bit;
when DP_150K_PU = 1, the switch is closed and the 150 k pull-up resistor is connected to the DP line.
The SW_DP3 switch defaults to a CLOSED state when power is applied to the device.
One DP and two DM pull-down resistors are also integrated. The Rdp_pd pull-down on the DP line is
switched in and out via the DP_PD bit (switched in if DP_PD = 1). The Rdm_pd pull-down on the DM
line is switched in and out via the DM_PD bit (switched in if DM_PD = 1). Rdp_pd and Rdm_pd are both
about 20 kΩ (14.25 to 24.8 kΩ), in accordance with the USB ECN for Pull-Up/Pull-Down Resistor. At
power up, both pull-downs are switched out. A 2.5 MΩ (±1.5 MΩ) pull-down resistor on the DM line is
connected by default and is automatically disconnected in mono and stereo audio modes (MC13883
MODE[2:0] of 100 or 101).
The variable 1.5 kΩ DP pull-up and DP/DM 20 kΩ pull-downs are disconnected from the DP and DM
lines during transmit. This is controlled via the TXENB line, such that when the transceiver is in transmit
mode (TXENB=0), the internal control signals are overridden and the pull-up / pull-downs are
disconnected. This is done to save battery power. If the bit PULLOVR = 0 this function is disabled.
In addition, the SE0_CONN bit is provided to automatically connect the variable 1.5 kΩ DP pull-up
resistor when SE0 is detected.
The block diagram in Figure 10 illustrates the variable DP 1.5 kΩ pull-up control circuit.
USB_EN
Timer output goes high when the timer is
enabled and goes low when the timer expires
USB_CNTRL
SRP Timer
(7.5msec)
EN
DP_SRP
DP_1K5_PU
DP_1K5PU_EN
PULLOVR
SE0_CONN
SE0 Decoder Out
TXENB
Figure 10. DP Pull-Up Control Circuit
This block diagram describes functionality. It is not intended to describe the actual circuit implementation
to be used.
MC13883 Technical Data, Rev. 3
34
Freescale Semiconductor