MC13883_10 Datasheet, PDF (17/64 Pages) Freescale Semiconductor, Inc – Integrated Charger USB Interface

Power Architecture
**** For the purpose of this table, when the BP Regulator / BP_FET column indicates an “ON” condition, the BP regulator is ON
if BP_SWITCH=0 (the BP Regulator is being used as a regulator). If BP_SWITCH=1 (indicating that the BP Regulator is acting
as a switch) then an “ON” in this column indicates that the BP_FET should be driven low. An “OFF” condition in this column
indicates that the BP regulator should be OFF (BP_SWITCH=0) or the BP_FET should be driven high (BP_SWITCH=1).
4.2.6 ICHRG Output
The ICHRG pin outputs either a voltage that is proportional to the current through Rs, the sense resistor,
or outputs a voltage that is proportional to the ID pin voltage.
When the Charge regulator is enabled, the ICHRG pin outputs a voltage that is proportional to the current
through Rs (from ISENSE to either BP or BATTP). When Reverse mode is enabled (RVRS_MODE = 1),
the ICHRG pin outputs a voltage that is proportional to the current through Rs (from either BP or BATTP
to ISENSE). This voltage is scaled from 0 to 2.3 V for currents from 0 to 1.8 A (full scale). The accuracy
of the ICHRG voltage should be ±10% of the actual charge current (after scaling) for charge currents
greater than 100 mA. For charge currents less than 100 mA, the accuracy requirement is ±10 mA compared
to the actual charge current.
If both the Charge Regulator and Reverse mode are disabled, the ICHRG pin outputs a voltage that is
proportional to the ID pin.
In idle mode, the MC13883 IC draws extra current when the MUX associated with the ICHRG pin is
enabled. This extra current is significant enough that standby time will be affected. To disable drive to this
pin, the ID_ICHRG_MUX_ENB can be asserted as listed in Table 50, Register 04 - Power Control 1 as
Bit 4.
The ID pin voltage or the CHRG_I current will not be able to be read when this pin is disabled. When the
MUX is disabled, the ICHRG pin is high impedance.
The ICHRG pin will have an output impedance of a maximum of 1.5 kΩ for load currents of 10 uA or less.¹
Table 10. Charge Control Logic Table
Signal
ICHRG
ICHRG
ICHRG
Condition
Input Range
Charge Regulator Enabled Icharge =
0 – 1.8A
RVRS_MODE = 1
Idischarge =
0 – 1.8A
ICHRG[3:0] = 0 and
RVRS_MODE = 1
ID = 0 to 5V
Equation
Icharge*(2.3V/1.8A)
Idischarge*(2.3V/1.8A)
ID Voltage*0.9
Tolerance
+/- 50 mV for Icharge ≤ 391mA,
+/- 10% for Icharge > 391mA
+/- 50 mV for Icharge < 391 mA,
+/- 10% for Icharge > 391 mA
+ 75 mV/-3% for ID < 1.0 V,
+/- 3% for 1.0 V < ID < 2.2 V,
ICHRG = 2.2 V to 2.5 V for ID = 5.0 V
1. For version 3.1, the ICHRG output impendance in ID mode is ~50 kΩ.
MC13883 Technical Data, Rev. 3
Freescale Semiconductor
17