K61P144M150SF3 Datasheet, PDF (30/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
f_{loc_low}
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
f_{ints_t}
f_{loc_high} Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
f_{ints_t}
FLL
f_{fll_ref} FLL reference frequency range
31.25
f_dco
DCO output
Low range (DRS=00)
20
frequency range
640 × f_{fll_ref}
Mid range (DRS=01)
40
1280 × f_{fll_ref}
Mid-high range (DRS=10)
60
1920 × f_{fll_ref}
High range (DRS=11)
80
2560 × f_{fll_ref}
f_{dco_t_DMX3} DCO output
2
frequency
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
2929 × f_{fll_ref}
J_{cyc_fll} FLL period jitter
—
• f_VCO = 48 MHz
• f_VCO = 98 MHz
—
J_{acc_fll} FLL accumulated jitter of DCO output over a 1µs
—
time window
t_{fll_acquire} FLL target frequency acquisition time
—
PLL0,1
f_{pll_ref} PLL reference frequency range
8
f_{vcoclk_2x} VCO output frequency
180
f_vcoclk PLL output frequency
90
f_{vcoclk_90} PLL quadrature output frequency
90
I_pll
PLL operating current (fast)
—
Typ.
—
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
180
150
TBD
—
—
—
—
—
TBD
Max.
—
—
39.0625
25
50
75
100
—
—
—
—
—
—
—
1
16
360
180
180
—
Table continues on the next page...
Unit
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ms
MHz
MHz
MHz
MHz
µA
Notes
2, 3
4, 5
6
7
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
30
Preliminary
Freescale Semiconductor, Inc.