K61P144M150SF3 Datasheet, PDF (27/82 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 13. JTAG voltage range electricals (continued)
Symbol
J3
Description
TCLK clock pulse width
• JTAG
• CJTAG
J4
TCLK rise and fall times
J5
TMS input data setup time to TCLK rise
• JTAG
• CJTAG
J6
TDI input data setup time to TCLK rise
J7
TMS input data hold time after TCLK rise
• JTAG
• CJTAG
J8
TDI input data hold time after TCLK rise
J9
TCLK low to TMS data valid
• JTAG
• CJTAG
J10
TCLK low to TDO data valid
J11
Output data hold/invalid time after clock edge¹
Min.
Max.
Unit
100
—
ns
200
—
ns
—
ns
—
1
ns
53
—
ns
112
8
—
ns
3.4
—
ns
3.4
3.4
—
ns
—
48
ns
85
—
48
ns
—
3
ns
1. They are common for JTAG and CJTAG.
TCLK (input)
J2
J3
J3
J4
J4
Figure 6. Test clock input timing
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
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