MC9S08QE32 Datasheet, PDF (3/44 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

1 MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08QE32 MCU.
MCU Block Diagram
HCS08 CORE
BKGD/MS
DEBUG MODULE (DBG)
CPU
BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
IRQ
POWER MANAGEMENT
COP
IRQ
LVD
USER FLASH
(MC9S08QE32 = 32768 BYTES)
(MC9S08QE16 = 16384 BYTES)
REAL-TIME COUNTER
(RTC)
IIC MODULE (IIC)
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI1)
SERIAL COMMUNICATIONS
INTERFACE MODULE(SCI2)
SERIAL PERIPHERAL
INTERFACE MODULE(SPI)
SCL
SDA
RxD1
TxD1
RxD2
TxD2
SS
MISO
MOSI
SPSCK
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBI1P3/SCL/ADP3
PTA2/KBI1P2/SDA/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1–
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTB3/KBI1P7/MOSI/ADP7
PTB2/KBI1P6/SPSCK/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
USER RAM
(MC9S08QE32 = 2048 BYTES)
(MC9S08QE16 = 1024 BYTES)
3-CHANNEL TIMER/PWM
MODULE (TPM1)
50.33 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSCVLP)
V_SS
V_DD
VOLTAGE REGULATOR
V_SSAD/V_REFL
V_DDAD/V_REFH
V_REFL
V_REFH
EXTAL
XTAL
3-CHANNEL TIMER/PWM
MODULE (TPM2)
6-CHANNEL TIMER/PWM
MODULE (TPM3)
V_SSAD
V_DDAD
ANALOG COMPARATOR
(ACMP1)
V_SSAD
V_DDAD
ANALOG COMPARATOR
(ACMP2)
10-CHANNEL, 12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC12)
TPM1CLK
TPM1CH2-TPM1CH0
TPM2CLK
TPM2CH2-TPM2CH0
TPM3CLK
TPM3CH5-TPM3CH0
ACMP1O
ACMP1–
ACMP1+
ACMP2O
ACMP2–
ACMP2+
ADP9-ADP0
PTC7/TxD2/ACMP2-
PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
PTC0/TPM3CH0
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3
PTD2/KBI2P2
PTD1/KBI2P1
PTD0/KBI2P0
PTE7/TPM3CLK
KEYBOARD INTERRUPT
MODULE (KBI1)
KBI1P7-KBI1P0
PTE6
PTE5
KEYBOARD INTERRUPT
MODULE (KBI2)
KBI2P7-KBI2P0
PTE4
PTE3/SS
PTE2/MISO
pins not available on 28-pin packages
pins not available on 28-pin or 32-pin packages
pins not available on 28-pin, 32-pin, or 44-pin packages
PTE1/MOSI
PTE0/TPM2CLK/SPSCK
Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device.
When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 28-pin packages: V_SSAD/V_REFL and V_DDAD/V_REFH are double bonded to V_SS and V_DD respectively.
The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins.
Figure 1. MC9S08QE32 Series Block Diagram
MC9S08QE32 MCU Series Data Sheet, Rev. 1
Freescale Semiconductor
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