MC9S08LG32 Datasheet, PDF (29/47 Pages) Freescale Semiconductor, Inc – 8-bit HCS08 Central Processor Unit (CPU)

2.11 AC Characteristics
This section describes timing characteristics for each peripheral system.
Electrical Characteristics
2.11.1 Control Timing
Table 14. Control Timing
Num C
Rating
Symbol
Min
Typ¹
Max Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2 D Internal low power oscillator period
3 D External reset pulse width²
t_LPO
700
t_extrst
100
—
1300 μs
—
—
ns
4 D Reset low drive
t_rstdrv
66 x t_cyc
—
—
ns
5 D BKGD/MS setup time after issuing background debug t_MSSU
500
force reset to enter user or BDM modes
—
—
ns
6 D BKGD/MS hold time after issuing background debug
t_MSH
100
force reset to enter user or BDM modes ³
—
—
μs
7 D IRQ pulse width
Asynchronous path²
Synchronous path⁴
t_ILIH
100
—
t_IHIL
1.5 x t_cyc
—
ns
—
—
8 D Keyboard interrupt pulse width
Asynchronous path²
Synchronous path⁴
t_ILIH
100
—
t_IHIL
1.5 x t_cyc
—
ns
—
—
9
C Port rise and fall time — (load = 50 pF)^{5, 6}
ns
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_Rise
—
t_Fall
—
3
—
30
—
1 _{Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request.}
3 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
4 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C.}
6 _{Except for LCD pins in Open Drain mode.}
RESET PIN
t_extrst
Figure 19. Reset Timing
MC9S08LG32 Series Data Sheet, Rev. 4
Freescale Semiconductor
29
Preliminary - Subject to Change Without Notice