MC9S08LG32 Datasheet, PDF (1/47 Pages) Freescale Semiconductor, Inc – 8-bit HCS08 Central Processor Unit (CPU)

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08LG32
Rev. 4, 2/2009
MC9S08LG32 Series
Covers: MC9S08LG32 and
MC9S08LG32
MC9S08LG16
80-LQFP
Case 917A
64-LQFP
Case 840F
14 mm × 14 mm
10 mm × 10 mm
Features
48-LQFP
• 8-bit HCS08 Central Processor Unit (CPU)
Case 932
– Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature
7 mm × 7mm
range of –40 °C to 85 °C and –40 °C to 105 °C
– On-chip in-circuit emulator (ICE) debug module containing
– HCS08 instruction set with added BGND instruction
three comparators and nine trigger modes; eight deep FIFO
– Support for up to 32 interrupt/reset sources
for storing change-of-flow addresses and event-only data;
• On-Chip Memory
debug module supports both tag and force breakpoints
– 32 KB or 18 KB dual array flash; read/program/erase ^{• Peripherals}
over full operating voltage and temperature
– LCD — Up to 4 × 41 or 8 × 37 LCD driver with internal
– 1984 byte random access memory (RAM)
charge pump.
– Security circuitry to prevent unauthorized access to
– ADC — Up to 16-channel, 12-bit resolution; 2.5 μs
RAM and flash contents
conversion time; automatic compare function; temperature
• Power-Saving Modes
sensor; internal bandgap reference channel; runs in stop3 and
– Two low-power stop modes (stop2 and stop3)
can wake up the system; fully functional from 5.5 V to 2.7 V
– Reduced-power wait mode
– SCI — Full duplex non-return to zero (NRZ); LIN master
– Peripheral clock gating register can disable clocks to
extended break generation; LIN slave extended break
unused modules, thereby reducing currents
detection; wakeup on active edge
– Low power on-chip crystal oscillator (XOSC) that can ^{– SPI — Full-duplex or single-wire bidirectional;}
be used in low-power modes to provide accurate clock
double-buffered transmit and receive; master or slave mode;
source to real time counter and LCD controller
MSB-first or LSB-first shifting
– 100 μs typical wakeup time from stop3 mode
– IIC — With up to 100 kbps with maximum bus loading;
• Clock Source Options
multi-master operation; programmable slave address;
– Oscillator (XOSC) — Loop-control Pierce oscillator;
interrupt driven byte-by-byte data transfer; supports
crystal or ceramic resonator range of 31.25 kHz to
broadcast mode and 10-bit addressing
38.4 kHz or 1 MHz to 16 MHz
– TPMx — One 6 channel and one 2 channel; selectable input
– Internal Clock Source (ICS) — Internal clock source
capture, output compare, or buffered edge or center-aligned
module containing a frequency-locked-loop (FLL)
PWM on each channel
controlled by internal or external reference; precision
– MTIM — 8-bit counter with match register; four clock
trimming of internal reference allows 0.2% resolution
sources with prescaler dividers; can be used for periodic
and 2% deviation over temperature and voltage; supports
wakeup
bus frequencies from 1 MHz to 20 MHz.
– RTC — 8-bit modulus counter with binary or decimal based
• System Protection
prescaler; three clock sources including one external source;
– COP reset with option to run from dedicated 1 kHz
can be used for time base, calendar, or task scheduling
internal clock or bus clock
functions
– Low-voltage warning with interrupt
– KBI — One keyboard control module capable of supporting
– Low-voltage detection with reset
8 × 8 keyboard matrix
– Illegal opcode detection with reset
– IRQ — External pin for wakeup from low-power modes
– Illegal address detection with reset
• Input/Output
– Flash and RAM protection
– 39, 53, or 69 GPIOs
• Development Support
– 8 KBI and 1 IRQ interrupt with selectable polarity
– Single-wire background debug interface
– Hysteresis and configurable pullup device on all input pins;
– Breakpoint capability to allow single breakpoint setting
configurable slew rate and drive strength on all output pins.
during in-circuit debugging (plus two more breakpoints ^{• Package Options}
in on-chip debug module)
– 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Preliminary - Subject to Change Without Notice