MC20XS4200 Datasheet, PDF (29/60 Pages) Freescale Semiconductor, Inc – Dual 24 V, 20 mOhm High Side Switch

in and regardless the values of the other bits in this register).
Next, a second data word must be received within the timeout
period (t_WDTO = 310 ms typ.) to be able to change any SPI
register contents. Upon entering Normal mode, the FSOB pin
returns to logic high and previously set faults and SPI
registers are reset, except bits POR, PARALLEL and fault
bits of latchable faults that had actually been latched.
FAULT MODE
The device enters Fault mode when any of the following
faults occurs in Normal or Fail-safe mode:
• Over-temperature fault, (latchable fault)
• Over-current fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to V_PWR in OFF state (default: disabled)
• Open-load fault in OFF state (default: disabled)
• Open-load fault in ON state (default: disabled)
• External Clock Failure (default: enabled)
• Over-voltage fault (enabled by default)
• Under-voltage fault, (latchable fault)
The Fault Status pin (FSB) asserts a fault occurrence on
any channel in real time (active low). Additionally, the
assigned fault bit in the STATR_s or FAULTR_s register is
set to one. Conversely to the FSB pin, a fault bit remains set
until the corresponding register is read, even if the fault has
disappeared. These bits can be read via the SO pin. Fault
occurrence will also result in a turn-off of the incurred
channel, except for the following faults: Open-load (On and
Off state), External Clock Failure and Output(s) shorted to
V_PWR. Under and Over-voltage occurrence will cause
simultaneous turn-off of both channels. Details on the
device’s behavior after the occurrence of one of the above
faults can be found inProtection and Diagnostic Features.
Fault mode (Operation and Operating Modes) is entered
when:
• V_PWR (+V_DD) were within the normal voltage range, and
• wake-up = 1, and
• fail-safe = X, and
• fault = 1 (see Going from Normal to Fail-safe, Fault or
Sleep Mode)
Resetting FAULT bits
Registers STATR_s and FAULTR_s contain global and
channel-specific fault information. Reading the register the
fault bit is contained in will clear it, provided failure cause
disappearance was detected and the fault wasn’t latched.
Entering Fault Mode from Fail-safe Mode
When a Fault occurs in Fail-safe mode, the device is in
Fault/Fail-safe mode and behaves according to the
description of fault mode. However, SPI registers remain
reset and can not be accessed. Only the Direct Inputs control
the channels.
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
Returning from Fault Mode to Fail-safe Mode
When disappearance of the fault previously produced in Fail-
safe mode has been detected, the device returns to Fail-safe
mode and behaves accordingly. FSB goes high, but the auto-
retry counter is not reset. Latched faults are not delatched.
SPI registers remain reset.
LATCHABLE FAULTS
An auto-retry function (see Auto-retry) controls how the
device responds to the so-called latchable faults. Latchable
faults are: over-current (OC), severe short-circuit (SC), over-
temperature (OT), and under-voltage (UV). If a latchable fault
occurs, the channel is turned off, the FSB terminal goes low,
and the assigned fault bit is set. These bits can not be reset
before the next turn-on event is generated by auto-retry.
Next, the channel will automatically be turned on at a
programmable interval (provided auto-retry was enabled and
the channel wasn’t latched).
If the failure disappears prior to the expiration of the
available amount of auto-retries, the FSB pin automatically
returns to logic [1], but the fault bit remains set. It can then still
be reset by reading the SPI register it is contained in.
However, the fault actually gets latched if the failure cause
hasn’t disappeared at the first turn-on event following
expiration of the available amount of auto-retries (see Auto-
retry). In that case, the channel gets latched and the FSB
terminal remains low. The fault bit can not be reset by reading
out the associated SPI register prior to performing a delatch
sequence (Fault Delatching).
Fault Delatching
To delatch a latched channel and be able to turn it on
again, a delatch sequence must be executed after
disappearance of the failure cause. Delatching will also allow
to reset the fault bit of latched faults (see Resetting FAULT
bits). To reset the FSB pin, both channels must be delatched.
Delatching is achieved either by alternating the state of the
channels’ fault control signal fc[x] (generating a 1_0_1
sequence), or by resetting the auto-retry counter (provided
retry is enabled). See Reset of the Auto-retry Counter).
Delatching then actually occurs at the rising edge of the turn-
on event.
Signal fc[x] is an internal signal used by the device’s
internal logic circuitry to control the diagnostic functions. The
value of fc[x] depends on the state of the variables IN_ON[x],
DIR_dis[x] and ON[x] and is expressed as follows:
fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1)
Alternating the fc[x] signal is achieved differently according
to the way the user controls the device.
• In direct-input controlled mode (DIR_dis_s = 0), the IN[x]
pin must be set low, remain low for at least t_IN seconds,
and set high again (be switched On). This might happen
automatically when operating at frequencies f<4.0 Hz.
Analog Integrated Circuit Device Data
Freescale Semiconductor
20XS4200
29