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MC9S08SH8CSC Datasheet, PDF (266/341 Pages) Freescale Semiconductor, Inc – MC9S08SH8 Datasheet | |||
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Chapter 16 Timer/PWM Module (S08TPMV3)
16.6.2.2.3 PWM End-of-Duty-Cycle Events
For channels conï¬gured for PWM operation there are two possibilities. When the channel is conï¬gured
for edge-aligned PWM, the channel ï¬ag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is conï¬gured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel ï¬ag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The ï¬ag is cleared by the two-step sequence
described Section 16.6.2, âDescription of Interrupt Operation.â
16.7 The Differences from TPM v2 to TPM v3
1. Write to TPMxCNTH:L registers (Section 16.3.2, âTPM-Counter Registers
(TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7]
Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter
(TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared
in this case.
2. Read of TPMxCNTH:L registers (Section 16.3.2, âTPM-Counter Registers
(TPMxCNTH:TPMxCNTL))
â In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the
TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was
read before the BDM mode became active, then any read of TPMxCNTH:L registers during
BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the
frozen TPM counter value.
â This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear
this read coherency mechanism.
3. Read of TPMxCnVH:L registers (Section 16.3.5, âTPM Channel Value Registers
(TPMxCnVH:TPMxCnVL))
â In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the
TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read
before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM
mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in
the TPMxCnVH:L registers.
â This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to
TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency
mechanism.
4. Write to TPMxCnVH:L registers
â Input Capture Mode (Section 16.4.2.1, âInput Capture Mode)
In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the
TPM v2 allows these writes.
â Output Compare Mode (Section 16.4.2.2, âOutput Compare Mode)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
262
Freescale Semiconductor
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