MC9S08PA60 Datasheet, PDF (26/35 Pages) Freescale Semiconductor, Inc – MC9S08PA60 Series

Peripheral operating requirements and behaviors
Table 15. SPI slave mode timing
Nu Symbol Description
m.
1
f_op
Frequency of operation
Min.
0
Max.
f_Bus/4
Unit
Hz
2
t_SPSCK SPSCK period
4 x t_Bus
—
ns
3
t_Lead Enable lead time
1
—
t_Bus
4
t_Lag
Enable lag time
1
—
t_Bus
5
t_WSPSCK Clock (SPSCK) high or low time
t_Bus - 30
—
ns
6
t_SU
Data setup time (inputs)
15
—
ns
7
t_HI
Data hold time (inputs)
25
—
ns
8
t_a
Slave access time
—
t_Bus
ns
9
t_dis
Slave MISO disable time
—
t_Bus
ns
10
t_v
Data valid (after SPSCK edge)
11
t_HO
Data hold time (outputs)
12
t_RI
Rise time input
t_FI
Fall time input
13
t_RO
Rise time output
t_FO
Fall time output
—
25
ns
0
—
ns
—
t_Bus - 25
ns
—
25
ns
Comment
f_Bus is the bus clock as
defined in .
t_Bus = 1/f_Bus
—
—
—
—
—
Time to data active from
high-impedance state
Hold time to high-
impedance state
—
—
—
—
SS
(INPUT)
SPSCK
(CPOL = 0)
(INPUT)
SPSCK
(CPOL = 1)
(INPUT)
8
MISO
(OUTPUT)
2
12
3
5
5
12
10
nsoetee
SLAVE MSB ^{BIT 6 . . . 1}
13 4
13
9
11
11
SLAVE LSB OUT
SEE
NOTE
MOSI
(INPUT)
6
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined!
Figure 15. SPI slave mode timing (CPHA = 0)
MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.
26
Freescale Semiconductor, Inc.