MC9S08SE8 Datasheet, PDF (25/38 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit

3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
Electrical Characteristics
3.10.1 Control Timing
Table 13. Control Timing
Num C
Rating
Symbol
Min
Typical¹ Max Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
2 D Internal low power oscillator period
3 D External reset pulse width²
4 D Reset low drive³
5
D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
f_Bus
DC
—
10
MHz
t_LPO
700
—
1300 μs
t_extrst
100
—
—
ns
t_rstdrv
34 × t_cyc
—
—
ns
t_MSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes⁴
t_MSH
100
—
—
μs
IRQ pulse width
7
D
Asynchronous path²
Synchronous path⁵
t_ILIH, t_IHIL
100
1.5 × t_cyc
—
—
ns
Pin interrupt pulse width
8
D
Asynchronous path²
Synchronous path⁵
t_ILIH, t_IHIL
100
1.5 × t_cyc
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁶
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_Rise, t_Fall
—
t_Rise, t_Fall
—
40
—
ns
75
11
—
ns
35
1 _{Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of tcyc.}
4 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
5 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
6 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 125 °C.}
RESET PIN
t_extrst
Figure 19. Reset Timing
MC9S08SE8 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
25