|
MC9S12P64VLHR Datasheet, PDF (235/566 Pages) Freescale Semiconductor, Inc – MC9S12P128 Reference Manual | |||
|
◁ |
S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.22 S12CPMU Protection Register (CPMUPROT)
This register protects the clock conï¬guration registers from accidental overwrite:
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC
0x02FB
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-29. S12CPMU Protection Register (CPMUPROT)
0
PROT
0
Field
0
PROT
Description
Clock Conï¬guration Registers Protection Bit â This bit protects the clock conï¬guration registers from
accidental overwrite (see list of affected registers above).
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0 Protection of clock conï¬guration registers is disabled.
1 Protection of clock conï¬guration registers is enabled. CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL,
CPMUIRCTRIMH/L and CPMUOSC registers are not writable.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
235
|
▷ |