MC9S12P64VLHR Datasheet, PDF (208/566 Pages) Freescale Semiconductor, Inc – MC9S12P128 Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
0x0036
7
6
5
4
3
2
1
0
R
0
0
0
W
POSTDIV[4:0]
Reset
0
0
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 7-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect.
If PLL is locked (LOCK=1)
f _PLL = ₍---_P----_O-----_S-^f--_T-^V---_D-^C----_I-^O-_V------₊-----₁---₎
If PLL is not locked (LOCK=0) f _PLL = ^f---^V----₄-^C----^O---
If PLL is selected (PLLSEL=1) f _bus = ^f---^P---₂-^L---^L--
7.3.2.4 S12CPMU Flags Register (CPMUFLG)
This register provides S12CPMU status bits and flags.
0x0037
7
R
RTIF
W
6
PORF
5
LVRF
4
LOCKIF
3
LOCK
2
ILAF
1
OSCIF
0
UPOSC
Reset
0
Note 1
Note 2
0
0
Note 3
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
= Unimplemented or Reserved
Figure 7-7. S12CPMU Flags Register (CPMUFLG)
Read: Anytime
S12P-Family Reference Manual, Rev. 1.13
208
Freescale Semiconductor