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MC9S08GT16AMFBE Datasheet, PDF (226/300 Pages) Freescale Semiconductor, Inc – MC9S08GT16A/GT8A Features | |||
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Analog-to-Digital Converter (S08ATDV3)
7
6
5
4
3
2
1
0
R ATDPU
DJM
RES8
SGN
PRS
W
Reset
0
0
0
0
0
0
0
0
Figure 14-3. ATD Control Register (ATDC)
Field
7
ATDPU
6
DJM
5
RES8
4
SGN
3:0
PRS
Table 14-2. ATDC Field Descriptions
Description
ATD Power Up â This bit provides program on/off control over the ATD, reducing power consumption when the
ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress.
0 Disable the ATD and enter a low-power state.
1 ATD functionality.
Data Justiï¬cation Mode â This bit determines how the 10-bit conversion result data maps onto the ATD result
register bits. When RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATDRH.
For left-justiï¬ed mode, result data bits 9â2 map onto bits 7â0 of ATDRH, result data bits 1 and 0 map onto ATDRL
bits 7 and 6, where bit 7 of ATDRH is the most signiï¬cant bit (MSB).
For right-justiï¬ed mode, result data bits 9 and 8 map onto bits 1 and 0 of ATDRH, result data bits 7â0 map onto
ATDRL bits 7â0, where bit 1 of ATDRH is the most signiï¬cant bit (MSB).
The effect of the DJM bit on the result is shown in Table 14-3.
0 Result register data is left justiï¬ed. See Figure 14-4.
1 Result register data is right justiï¬ed. See Figure 14-5.
ATD Resolution Select â This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD
converter has the accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit
resolution will map result data bits 9-2 onto ATDRH bits 7-0.
The effect of the RES8 bit on the result is shown in Table 14-3.
0 10-bit resolution selected.
1 8-bit resolution selected.
Signed Result Select â This bit determines whether the result will be signed or unsigned data. Signed data is
represented as 2âs complement data and is achieved by complementing the MSB of the result. Signed data mode
can be used only when the result is left justiï¬ed (DJM = 0) and is not available for right-justiï¬ed mode (DJM = 1).
When a signed result is selected, the range for conversions becomes â512 ($200) to 511 ($1FF) for 10-bit
resolution and â128 ($80) to 127 ($7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in Table 14-3.
0 Left justiï¬ed result data is unsigned.
1 Left justiï¬ed result data is signed.
Prescaler Rate Select â This ï¬eld of bits determines the prescaled factor for the ATD conversion clock.
Table 14-4 illustrates the divide-by operation and the appropriate range of bus clock frequencies.
76543210
76543210
9
RESULT
0
ATDRH
ATDRL
Figure 14-4. Left-Justiï¬ed Mode
76543210
9
ATDRH
76543210
RESULT
0
ATDRL
Figure 14-5. Right-Justiï¬ed Mode
MC9S08GT16A/GT8A Data Sheet, Rev. 1
226
Freescale Semiconductor
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