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MC9S08GT16AMFBE Datasheet, PDF (215/300 Pages) Freescale Semiconductor, Inc – MC9S08GT16A/GT8A Features | |||
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13.4 Functional Description
This section provides a complete functional description of the IIC module.
Inter-Integrated Circuit (S08IICV1)
13.4.1 IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
⢠START signal
⢠Slave address transmission
⢠Data transfer
⢠STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described brieï¬y in the following sections and illustrated in Figure 13-8.
MSB
LSB
SCL
1 2 34 5 6 78 9
MSB
LSB
1 2 34 5 6 78 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX D7 D6 D5 D4 D3 D2 D1 D0
START
SIGNAL
CALLING ADDRESS
READ/ ACK
WRITE BIT
MSB
LSB
SCL
1 2 34 5 67 89
DATA BYTE
NO STOP
ACK SIGNAL
BIT
MSB
LSB
1 234 5 678 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
SIGNAL
CALLING ADDRESS
READ/ ACK REPEATED
WRITE BIT START
SIGNAL
NEW CALLING ADDRESS
READ/ NO STOP
WRITE
ACK
BIT
SIGNAL
Figure 13-8. IIC Bus Transmission Signals
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
215
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