MC9S08SV16 Datasheet, PDF (22/40 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Electrical Characteristics
2 _{When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz}
to 39.0625 kHz.
3 _{See crystal or resonator manufacturer’s recommendation.}
4 _{This parameter is characterized and not tested on each device.}
5 _{Proper PC board layout procedures must be followed to achieve specifications.}
6 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit}
is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
7 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a
given interval.
EXTAL
XOSC
R_F
XTAL
R_S
Crystal or Resonator
C₁
C₂
Figure 15. Typical Crystal or Resonator Circuit
1.00%
0.50%
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
TBD ^-1.00%
-1.50%
-2.00%
Temperature
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
MC9S08SV16 Series Data Sheet, Rev. 2
22
Freescale Semiconductor