MC9S08FL16 Datasheet, PDF (20/34 Pages) Freescale Semiconductor, Inc – 8-Bit S08 Central Processor Unit (CPU)

Electrical Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Num C
Characteristic
Symbol
Min Typical¹ Max Unit
Long term jitter of DCO output clock (averaged over 2 ms
13 C _{interval) 8}
C_Jitter
—
0.02
0.2 %f_dco
1 _{Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.}
2 _{When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of}
31.25 kHz to 39.0625 kHz.
3 _{See crystal or resonator manufacturer’s recommendation.}
4 _{This parameter is characterized and not tested on each device.}
5 _{Proper PC board layout procedures must be followed to achieve specifications.}
6 _{The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.}
7 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32}
bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If
a crystal/resonator is being used as the reference, this specification assumes it is already running.
8 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for
a given interval.
EXTAL
XOSC
R_F
XTAL
R_S
Crystal or Resonator
C₁
C₂
Figure 10. Typical Crystal or Resonator Circuit
MC9S08FL16 Series Data Sheet, Rev. 2
20
Freescale Semiconductor