MRF7S21210HR3 Datasheet, PDF (2/15 Pages) Freescale Semiconductor, Inc – RF Power Field Effect Transistors N-Channel Enhancement-Mode Lateral MOSFETs

Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22 - A114)
1C (Minimum)
Machine Model (per EIA/JESD22 - A115)
A (Minimum)
Charge Device Model (per JESD22 - C101)
IV (Minimum)
Table 4. Electrical Characteristics (T_C = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Off Characteristics
Zero Gate Voltage Drain Leakage Current
(V_DS = 65 Vdc, V_GS = 0 Vdc)
Zero Gate Voltage Drain Leakage Current
(V_DS = 28 Vdc, V_GS = 0 Vdc)
Gate - Source Leakage Current
(V_GS = 5 Vdc, V_DS = 0 Vdc)
I_DSS
—
—
10
μAdc
I_DSS
—
—
1
μAdc
I_GSS
—
—
1
μAdc
On Characteristics
Gate Threshold Voltage
(V_DS = 10 Vdc, I_D = 513 μAdc)
Gate Quiescent Voltage
(V_DS = 28 Vdc, I_D = 1400 mAdc)
Fixture Gate Quiescent Voltage ⁽¹⁾
(V_DD = 28 Vdc, I_D = 1400 mAdc, Measured in Functional Test)
Drain - Source On - Voltage
(V_GS = 10 Vdc, I_D = 5.13 Adc)
Dynamic Characteristics ⁽²⁾
Reverse Transfer Capacitance
(V_DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V_GS = 0 Vdc)
Output Capacitance
(V_DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V_GS = 0 Vdc)
Input Capacitance
(V_DS = 28 Vdc, V_GS = 0 Vdc ± 30 mV(rms)ac @ 1 MHz)
V_GS(th)
1.2
2
2.7
Vdc
V_GS(Q)
—
2.7
—
Vdc
V_GG(Q)
4
5.4
7
Vdc
V_DS(on)
0.1
0.2
0.3
Vdc
C_rss
—
2.02
—
pF
C_oss
—
257
—
pF
C_iss
—
516
—
pF
Functional Tests (In Freescale Test Fixture, 50 ohm system) V_DD = 28 Vdc, I_DQ = 1400 mA, P_out = 63 W Avg., f = 2112.5 MHz and f =
2167.5 MHz, Single - Carrier W - CDMA, 3GPP Test Model 1, 64 DPCH, 50% Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on
CCDF. ACPR measured in 3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Power Gain
G_ps
17
18.5
20.5
dB
Drain Efficiency
η_D
26
29
—
%
Output Peak - to - Average Ratio @ 0.01% Probability on CCDF
PAR
5.5
5.9
—
dB
Adjacent Channel Power Ratio
ACPR
—
- 33
- 31
dBc
Input Return Loss
IRL
—
- 15
-8
dB
1. V_GG = 2 x V_GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit
schematic.
2. Part internally matched both on input and output.
(continued)
MRF7S21210HR3 MRF7S21210HSR3
2
RF Device Data
Freescale Semiconductor