MCF5475EC Datasheet, PDF (19/34 Pages) Freescale Semiconductor, Inc – MCF547x ColdFire Microprocessor

SDRAM Bus
Table 13. DDR Timing Specifications (continued)
Symbol
Characteristic
Min
Max
Unit Notes
DD13 DQS input read preamble width (t_RPRE)
0.9
1.1
SDCLK
DD14 DQS input read postamble width (t_RPST)
0.4
0.6
SDCLK
DD15 DQS output write preamble width (t_WPRE)
0.25
—
SDCLK
DD16 DQS output write postamble width (t_WPST)
0.4
0.6
SDCLK
1 _{DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify.}
2 _{The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external}
reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at
the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal
Descriptions” chapter within the MCF547x Reference Manual.
3 _{SDCLK is one memory clock in (ns).}
4 _{Pulse width high plus pulse width low cannot exceed max clock period.}
5 _{Pulse width high plus pulse width low cannot exceed max clock period.}
6 _{Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,}
temperature, and voltage variations.
7 _{This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,}
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
8 _{The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data}
beats is valid for each subsequent SDDQS edge.
9 _{This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,}
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
10 _{Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data}
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
11 _{Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data}
line becomes invalid.
MCF547x ColdFire^® Microprocessor, Rev. 4
Freescale Semiconductor
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