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MCF5475EC Datasheet, PDF (1/34 Pages) Freescale Semiconductor, Inc – MCF547x ColdFire Microprocessor | |||
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Freescale Semiconductor
Data Sheet
Document Number: MCF5475EC
Rev. 4, 12/2007
MCF547x ColdFire®
Microprocessor
Supports MCF5470, MCF5471,
MCF5472, MCF5473, MCF5474, and
MCF5475
MCF547x
TEPBGAâ388
27 mm x 27 mm
Features list:
⢠ColdFire V4e Core
â Limited superscalar V4 ColdFire processor core
â Up to 266 MHz peak internal core frequency (410 MIPS
[Dhrystone 2.1] @ 266 MHz)
â Harvard architecture
â 32-Kbyte instruction cache
â 32-Kbyte data cache
â Memory Management Unit (MMU)
â Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
â Floating point unit (FPU)
â Double-precision conforms to IEE-754 standard
â Eight floating point registers
⢠Internal master bus (XLB) arbiter
â High performance split address and data transactions
â Support for various parking modes
⢠32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
â 66â133 MHz operation
â Supports DDR and SDR DRAM
â Built-in initialization and refresh
â Up to four chip selects enabling up to one GB of external
memory
⢠Version 2.2 peripheral component interconnect (PCI) bus
â 32-bit target and initiator operation
â Support for up to five external PCI masters
â 33â66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
⢠Flexible multi-function external bus (FlexBus)
â Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
â Up to six chip selects
â 33 â 66 MHz operation
⢠Communications I/O subsystem
â Intelligent 16 channel DMA controller
â Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
â Universal serial bus (USB) version 2.0 device controller
â Support for one control and six programmable
endpoints, interrupt, bulk, or isochronous
â 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
â Integrated physical layer interface
â Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
â I2C peripheral interface
â DMA Serial Peripheral Interface (DSPI)
⢠Optional Cryptography accelerator module
â Execution units for:
â DES/3DES block cipher
â AES block cipher
â RC4 stream cipher
â MD5/SHA-1/SHA-256/HMAC hashing
â Random Number Generator
⢠32-Kbyte system SRAM
â Arbitration mechanism shares bandwidth between
internal bus masters
⢠System integration unit (SIU)
â Interrupt controller
â Watchdog timer
â Two 32-bit slice timers alarm and interrupt generation
â Up to four 32-bit general-purpose timers, compare, and
PWM capability
â GPIO ports multiplexed with peripheral pins
⢠Debug and test features
â ColdFire background debug mode (BDM) port
â JTAG/ IEEE 1149.1 test access port
⢠PLL and clock generator
â 30 to 66.67 MHz input frequency range
⢠Operating Voltages
â 1.5V internal logic
â 2.5V DDR SDRAM bus I/O
â 3.3V PCI, FlexBus, and all other I/O
⢠Estimated power consumption
â Less than 1.5W (388 PBGA)
© Freescale Semiconductor, Inc., 2007. All rights reserved.
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