MCF5475EC Datasheet, PDF (12/34 Pages) Freescale Semiconductor, Inc – MCF547x ColdFire Microprocessor

Reset Timing Specifications
7 Reset Timing Specifications
Table 9 lists specifications for the reset timing parameters shown in Figure 10
Table 9. Reset Timing Specifications
Num
Characteristic
66 MHz CLKIN
Min Max
Units
R1¹
Valid to CLKIN (setup)
8
—
ns
R2
CLKIN to invalid (hold)
1.0
—
ns
R3
RSTI to invalid (hold)
1.0
—
ns
RSTI pulse duration
5
— CLKIN cycles
1 _{RSTI and FlexBus data lines are synchronized internally. Setup and hold}
times must be met only if recognition on a particular clock is required.
Figure 10 shows reset timing for the values in Table 9.
CLKIN
R1
RSTI
Mode Select
FlexBus
R1
R2
R3
NOTE:
Mode selects are registered on the rising clock edge before
the cycle in which RSTI is recognized as being negated.
Figure 10. Reset Timing
8 FlexBus
A multi-function external bus interface called FlexBus is provided on the MCF5472 with basic functionality to interface to
slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous
devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no
additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six
general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed
to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash
memories.
MCF547x ColdFire^® Microprocessor, Rev. 4
12
Freescale Semiconductor