MC9S08JS16 Datasheet, PDF (19/32 Pages) Freescale Semiconductor, Inc – Technical Data

Electrical Characteristics
3 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for
a given interval.
4 _{Jitter measurements are based upon a 48 MHz clock frequency.}
5 _{625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN}
bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge
and the sample point of a bit using 8 time quanta per bit.
6 _{Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG}
is already in lock, then the MCG may stay in lock.
7 _{Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.}
3.9 AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.9.1 Control Timing
Figure 13. Control Timing
Num C
Parameter
Symbol
Min
Typical¹
Max
Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
DC
—
2 D Internal low-power oscillator period
3
D
External reset pulse width²
(t_cyc = 1/f_{Self_reset})
t_LPO
700
—
t_extrst
1.5 × t_{Self_reset}
—
4 D Reset low drive
t_rstdrv
66 × t_cyc
—
5
D
Active background debug mode latch setup
time
t_MSSU
25
—
24
1300
—
—
—
MHz
μs
ns
ns
ns
6
D
Active background debug mode latch hold
time
t_MSH
25
—
—
ns
IRQ pulse width
7
D
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
1.5 × t_cyc
—
KBIPx pulse width
8
D
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
1.5 × t_cyc
—
Port rise and fall time (load = 50 pF)⁴
9
C
Slew rate control disabled (PTxSE = 0)
t_Rise, t_Fall
—
3
Slew rate control enabled (PTxSE = 1)
—
30
—
ns
—
ns
—
ns
—
1 _{Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not}
be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
MC9S08JS16 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
19