34652_07 Datasheet, PDF (17/26 Pages) Freescale Semiconductor, Inc – 2.0 A Negative Voltage Hot Swap Controller with Enhanced Programmability

FUNCTIONAL DEVICE OPERATION
PROTECTION FEATURES
The power dissipation in the device can be calculated as
follows:
P = I^2(LOAD) _* R_DS(ON)
OR
P = [T_J(max) - T_A(max)] / R_θJA
Combining the two equations:
I^2(LOAD) = [ T_J (max) - T_A(max)] / [R_{θJA *} R_DS(ON)] Eq 1
For example:
T_A(max) = 55°C
R_θJA = 51°C/W for a four-layer board
R_DS(ON) = 0.251 Ω at high temperatures
Then:
I^2(LOAD) = [ T_J (max) - 55°C] / [51°C/W _* 0.251 Ω]
I^2(LOAD) = [ T_J (max) - 55°C] / 12.80°C / A²
So if the overcurrent limit is 2.0 A, then the maximum
junction temperature is 106.2°C, which is well below the
thermal shutdown temperature that is allowed.
The previous explanation applies to steady state power
when the device is in normal operation. During the charging
process, the power is dominated by the I * V across the Power
MOSFET. When charging starts, the power in the Power
MOSFET rises up and reaches a maximum value of I * V, then
quickly ramps back down to the steady state level in a period
governed by the size of the load’s input capacitor that is being
charged and by the value of the charging current limit I_CHG.
In this case the instantaneous power dissipation is much
higher than the steady state case, but it is on for a very short
time.
For example:
I_CHG = 100 mA, the default value
C_LOAD = 400 µF, a very large capacitor
V_PWR = 80 V, worst case
Then:
The power pulse magnitude = I_{CHG *} V_PWR = 8.0 W
The power pulse duration = C_{LOAD *} V_PWR/I_CHG = 320 ms
Figure 17 displays the temperature profile of the device
under the instantaneous power pulse during the charging
process. Table 5 depicts thermal resistance values for
different board configurations.
60.0
50.0
40.0
30.0
20.0
10.0
0.0
0
100
200
300
400
TimTeim(em(imllis)e c)
Figure 17. Instantaneous Temperature Rise of an 8.0 W
Table 5. Thermal Resistance Data
Type
Junction to Ambient
Junction to Ambient
Junction to Ambient
Junction to Ambient
Condition
Symbol Value
Single-layer board (1s), per JEDEC JESD51-2 with board (JESD51-3) horizontal
R_θJA
103
Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal
R_θJMA
65
Single-layer board with a 300 mm² radiator pad on its top surface, not standard JEDEC —
69
Single-layer board with a 600 mm² radiator pad on its top surface, not standard JEDEC _—
65
Junction to Ambient ^{Four-layer board with a via for each thermal lead, not standard JEDEC}
—
51
Junction to Ambient Four-layer board with a 300 mm² radiator pad on its top surface and a full array of vias
—
47
between radiator pad and top surface, not standard JEDEC
Junction to Ambient ^{Four-layer board with a 600 mm2 radiator pad on its top surface and a full array of vias}
—
47
between radiator pad and top surface, not standard JEDEC
Junction to Board
Junction to Case
Junction to Package
Top
Thermal resistance between die and board per JEDEC JESD51-8
Thermal resistance between die and case top
Temperature difference between package top and junction per JEDEC JESD51-2
R_θJB
29
R_θJC
33
Ψ_JT
12
Junction to Lead
Thermal resistance between junction and thermal lead, not standard JEDEC
R_θJL
33
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Analog Integrated Circuit Device Data
Freescale Semiconductor
34652
17