IMX53AEC Datasheet, PDF (16/178 Pages) Freescale Semiconductor, Inc – Automotive and Infotainment Applications Processors

Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
UART-1
UART-2
UART-3
UART-4
UART-5
USB
VPU
WDOG-1
UART Interface Connectivity
Peripherals
USB Controller Connectivity
Peripherals
Video Processing Multimedia
Unit
Peripherals
Watch Dog
Timer
Peripherals
Each of the UART blocks supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd,
or none)
• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate
relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F
standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB supports USB2.0 480 MHz, and contains:
• One high-speed OTG sub-block with integrated HS USB PHY
• One high-speed host sub-block with integrated HS USB PHY
• Two identical high-speed Host modules
The high-speed OTG module, which is internally connected to the HS USB
PHY, is equipped with transceiver-less logic to enable on-board USB
connectivity without USB transceivers
All the USB ports are equipped with standard digital interfaces (ULPI, HS
IC-USB) and transceiver-less logic to enable onboard USB connectivity
without USB transceivers.
A high-performing video processing unit (VPU) version 3, which covers
many SD-level video decoders and SD-level encoders as a multi-standard
video codec engine as well as several important video processing such as
rotation and mirroring.
VPU Features:
• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit
rate
• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps
bit rate
• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate
• Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate
• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,
40 Mpixel/s bit rate for 4:4:4 format
• MPEG2¹ encode, Main-Main profile, up to D1 resolution, 15 Mbps bit
rate
• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate²
• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate²
• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate²
• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,
80 Mpixel/s bit rate for 4:2:2 format
The watch dog timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt
to the ARM core, and a second point evokes an external event on the
WDOG line.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
16
Freescale Semiconductor