IMX53AEC Datasheet, PDF (129/178 Pages) Freescale Semiconductor, Inc – Automotive and Infotainment Applications Processors

Electrical Characteristics
Table 84. SSI Transmitter Timing with Internal Clock (continued)
ID
SS17
SS18
SS19
SS42
SS43
SS52
Parameter
Min
(Tx) CK high to STXD high/low
—
(Tx) CK high to STXD high impedance
—
STXD rise/fall time
—
Synchronous Internal Clock Operation
SRXD setup before (Tx) CK falling
10.0
SRXD hold after (Tx) CK falling
0.0
Loading
—
Max
Unit
15.0
ns
15.0
ns
6.0
ns
—
ns
—
ns
25.0
pF
NOTE
• All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
• All timings are on Audiomux Pads when SSI is being used for data
transfer.
• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
129