MC9S08AW32CPUE Datasheet, PDF (140/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Internal Clock Generator (S08ICGV4)
R
W
Reset
Field
7:0
FLT
7
6
5
4
3
2
1
0
FLT
1
1
0
0
0
0
0
0
Figure 8-11. ICG Lower Filter Register (ICGFLTL)
Table 8-6. ICGFLTL Register Field Descriptions
Description
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete. The filter registers show the filter value (FLT).
8.3.6 ICG Trim Register (ICGTRM)
7
6
5
4
3
2
1
0
R
TRIM
W
POR
1
0
0
0
0
0
0
0
Reset:
U
U
U
U
U
U
U
U
U = Unaffected by MCU reset
Figure 8-12. ICG Trim Register (ICGTRM)
Table 8-7. ICGTRM Register Field Descriptions
Field
7
TRIM
Description
ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ±25%
adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.
8.4 Functional Description
This section provides a functional description of each of the five operating modes of the ICG. Also
discussed are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG
is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When
using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value
to ensure proper MCU operation.
MC9S08AW60 Data Sheet, Rev 2
140
Freescale Semiconductor