MC68882EI33A Datasheet, PDF (13/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

Freescale Semiconductor, Inc.
Table 5. DSACK Assertions
Data bus
A4
DSACKI
DSACKO
Comments
32-Bit
1
Low
32-Bit
o
Low
Low
High
Valid Data on D31-DO
Valid Data on D31-D16
16-Bit
x
Low
High
Valid Data on D31-D16 or D15-DO
8-Bit
x
High
Low
Valid Data on D31-D24,.D23-D16, D15-D8, or D7-DO
All
x
High
High
Insert Wait States in Current Bus Cycle
MC68882 following the rising edge of AS or DS, and both
DSACK lines are then three-stated (placed in the high-
impedance state) to avoid interference with the next bus
cycle.
RESET (RESET)
~~~~.j,
time and must conform to minimum
riod and pulse width times.
SENSE DEVICE (SENSE)
.:J;:::{:.Jy<~,:,~:!l
and m~~~~.~’’pe-
~!i*,t,!,,:V.*,>,,S$?k“~.:.,$$:$’‘~.,*y.w:~,$*t.~,.$.,,:...,;,,‘.<w.~,,~~,,~\.j:,.?\l~~.
This pin may be used optionally ~~~fi,$~ditional GND
pin or as as indicator to exte{~’~?$t~~dware that the
This active-low input signal causes the MC68882 to
MC68882 is present in the sys~$m$%~~ signal is internally
initialize the floating-point data registers to non-signaling
connected to the GND of t~:~~$~, but it is not necessary
not-a-numbers (NANs) and clears the floating-point con-
to connect it to the ext~w$$?ound
for correct device
trol, status, and instruction address registers.
operation. Ifa pullup rp~~$~iwhich should be Iargerthan
When performing a power-up reset, external circuitry
should keep the RESET line asserted for a minimum of
four clock cycles after VCC is within tolerance. This as-
sures correct initialization of the MC68882 when power
10 kohm) is conneqq~.at~*~%,xJ~~: _:s,<,:i,. pin location, external hard-
ware may sense, the~resence
.~,~~t$~}..}.
tem.
~owER
~gc~,bj ^{~~.t,$:.,7,$i:t!*:>+~:$N;D$.)}
of the MC68882 in a sys-
is applied, For compatibility with all M68000 Family de-
vices, 100 milliseconds should be used as the minimum.
,.\q,~.,*.,.:,,~,,..,
Thes%i~~ns provide the supply voltage and system ref-
When performing a reset of the MC68882 after VCC has
er%a$e Iekl for the internal circuitry of the MC68882, Care
been within tolerance for more than the initial ~ower-uo
..~~uf~ be taken to reduce the noise level on these pins
time, the RESET line must have an asserted p~lse width ,P,$~fi~ appropriate capacitive decoupling,
which is greater than two clock cycles. For compatibility _{‘~.*;,$.} ‘,*::>::$b*%s _?$:
with all M68000 Family devices, 10 clock cycles should I;,,_...-ho CONNECT (NC)
be used as the minimum.
.,<..(*’
,$,$
One pin of the MC68882 package is designated as a no
..,‘7!.,..!,$:,,,,
connect (NC). This pin position is reserved for future use
CLOCK (CLK)
i~,,!, .?*t.
by Motorola, and should not be used for signal routing
The MC68882 clock input is a ~L-com~#~W&~ignal
or connected to VCC or GND.
that is internally buffered for development~~,th~ ?nternal
clock signals, The clock input should ,Qd~$:&~%fi:stantfre-
SIGNAL SUMMARY
quency square wave with no stretchi~~~$~$haping tech-
Table 6 provides a summary of all the MC68882 signals
niques required. The clock should q~t~ ~ated offat anY
.,:~:,?,.’.. .sy>..,’
described in the above paragraphs.
t!;:>\ <.
\
SignaK<#a*eJ’o
:~i:i\y
Address Bus,~>’:$
{
Data Bus ‘$:$**~~#F
Size ,%~~>)~
?~$?$s~tro be
~,t:,,),.,.>‘.&~i,@S-elect
‘@:J‘;:~’%ad/Write
.$~,+~,\)?‘~:3.,
‘.“,t‘{$,!~~’ Data Strobe
~.~
Data Transfer
and Size Acknowledge
Reset
Clock
Sense Device
Power Input
Ground
Mnemonic
AO-A4
DO-DI 3
SIZE
G
m
Rim
m
DSACKO, DSACK1
RESET
CLK
SENSE
Vcc
GND
lnputiOutput
Input
Input/Output
Input
Input
Input
Input
Input
output
Input
Input
Input/Output
Input
Input
Active State
High
High
Low
Low
Low
High/Low
Low
Low
Low
—
Low
—
—
Three State
—
Yes
—
—
—
—
—
Yes
—
—
No
—
—
MC-
BR=/Rev.
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For More Information On This Product,
Go to: www.freescale.com
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MOTOROLA
13
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