MC68882EI33A Datasheet, PDF (12/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

....-
A4-AO
Oooox
Freescale Semiconductor, Inc.
Table 3. Coprocessor Intetiace
ADDRESS STROBE (AS)
Register Selection
This active-low input signal indicates that there is a
Offset
$00
Mdth
16
Type
Register
Read Response
valid address on the address bus, and both the chip select
(CS) and read/write (R~) signal lines are valid.
Ooolx
$02
16
Write Control
CHIP SELECT (CS)
Oolox
Oollx
Oloox
Ololx
Ollox
Olllx
1Ooxx
101OX
Iollx
11Oxx
Illxx
$04
$06
$08
$OA
$Oc
$OE
$10
$14
$16
$18
$lC
16
Read Save
16
R~ Restore
16
–
(Reserved)
16 Write Command
16
–
(Reserved)
16 Write Condition
32
Rfi Operand
16
Read Register Select
16
–
(Reserved)
32
Read Instruction Address
32
RR Operand Address
This active-low input signal enables the main processor
access to the MC68882 coprocessor interface registers.
When operating the MC68882 as a peripheral pro$essor,
the chip select decode is system dependent (i.~~~j~$the
chip select on any peripheral).
.\\!.+>’*“}:.,.i,.?~,?
READ/WRITE (R/~)
.?;.~l.\,;,,.\.~$.$\,.’.s.:,~*k.
!,.*’.;t>.,.Khi~+:.‘,.:.,‘,t3%!..,:“.:$~~~,,,
This input signal indicates the di~~8]o~#@Y a bus trans-
action (read/write) by the main~f~~~sbr.
A logic high
(1) indicates a read from the @8,@~, an~ a logic low
(0) indicates a w~te to the ~~~8&The
RN signal must
be valid when AS is as.s‘~X@.,..,+“\X.*l*@,-?$+,:)~$j.:!+
~:<.:.~,/,..,
DATA STROBE (DS,;)~’:.X>.tj~,,>,~+,ft,.$~
This active-lowin:~~~ignal
indicates that there is valid
When the MC68882 is configured to operate over an 8-
data on the d~~~:~ys during a write bus cycle.
bit data bus, the AO pin is used as an address signal for
byte accesses of the coprocessor interface registers. When
the MC68882 is configured to operate over a f16- or 32-
bit system data bus, both the AO and the SIZE pins are
strapped high and/or low as listed in Table 4.
‘?,
~Kese active-low, three-state output signals indicate
..?~,,c&hpletion of a bus cycle to the main processor. The
i$$it,~@8882 asserts b~h the DSACKO and DSACKI signals
Table
4. System
AO
—
Low
Data Bus Size Configuration
*$rS$$upon assertion of CS.
‘-l?+ _{If the bus cycle is a main processor read, the MC68882}
SIZE
Data Bus
,$~~$’ ^~,:i’$t
asserts DSACKO and DSACKI signals to indicate that the
Low
.; ‘>:,},
8-Bit _{..*.,.,t,*t,.,,.,,*,>:.,.}
information on the data bus is valid. (Both DSACK signals
may be asserted in advance of the valid data being placed
High
16-Bi~$$’Q$y‘?’
.,?, .. :.
on the bus. ) If the bus cycle is a main processor write to
High
High
3~*qk$;,.~’
the MC68882, DSACKO and DSACKI are used to acknowl-
.~~,;~y$.
,,,...:‘.\.\.~.J’~~:.i\,>
,,4>).‘ ‘%;V$~, $
edge acceptance of the data by the MC68882.
The MC68882 also uses DSACKO and DSACKI signals
DATA BUS (DO through D31 ) ~~” ‘“~~
to dynamically indicate to the MC68020/MC68030 the
This 32-bit, bidirectional, +~k~%%~bte bus serves as the
general purpose data,~~~h,~etween
the MC68020/
MC68030 and the MC~~&~.’’’Regardless of whether the
MC68882 is operat~d a~$~’coprocessor or a peripheral
processor, all in~,@$@o,gessor transfers of instruction in-
formation, op~r,~~d$$~ata, status information, and re-
quests for $~~J~@’&ccur as standard M68000 bus cycles.
The MQ@,*~will
operate over an 8-, 16-, or 32-bit
syste~%at%~,bbs. Depending upon the system data bus
conJ~@~~{a@n, both the AO and SIZE pins are configured
s~:~?t~a”lly for the applicable bus configuration. (Refer to
:$Q~*ESS BUS (AO through A4) and SIZE (SIZE) for fur-
‘&$#$rjdetails).
“port” size (system data bus width) on a cycle-by-cycle
basis, Depending upon which of the two DSACK pins are
asserted in a given bus cycle, the MC68020/MC68030 as-
sumes data has been transferred to/from an 8-, 16-, or
32-bit wide data port. Table 5 lists the DSACK assertions
that are used by the MC68882 for the various bus cycles
over the various system data bus configurations.
Table 5 indicates that all accesses over a 32-bit bus
where A4 equals zero are to 16-bit registers, The MC68882
implements all 16-bit coprocessor interface registers on
data lines D16-D31 (to eliminate the need for on-chip
multi plexers); however, the MC68020/MC68030 expects
16-bit registers that are located in a 32-bit port at odd
word addresses (Al = 1) to be implemented on data lines
SIZE (SIZE)
DO-DI 5. For accesses to these registers when configured
for 32-bit bus operation, the MC68882 generates DSACK
This active-low input signal is used in conjunction with
signals as listed in Table 5 to inform the MC68020/
the AO pin to configure the MC68882 for operation over
MC68030 of valid data on D16-D31 instead of DO-D15.
an 8-, 16-, or 32-bit system data bus. When the MC68882
An external holding resistor is required to maintain
is configured t~erate
over a 16- or 32-bit system data
both DSACKO and DSACKI high between bus cycles. In
bus, both the SIZE and AO pins are strapped high and/or
order to reduce the signal rise time, the DSACKO and
low as listed in Table 4.
DSACKI lines are actively pulled up (negated) by the
~:- ^...
r .:::.Y
For More Information On This Product,
Go to: www.freescale.com