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33879 Datasheet, PDF (12/24 Pages) Freescale Semiconductor, Inc – Configurable Octal Serial Switch with Open Load Detect Current Disable
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
SCLK
DI
DO
0.2 VDD
tLEAD
0.7 VDD
0.2 VDD
tDI(SU) tDI(HOLD)
0.7 VDD
0.2 VDD
MSB in
tDO(EN)
0.7 VDD
0.2 VDD
MSB out
tVALID
Figure 4. SPI Timing Diagram
tLAG
tDO(DIS)
LSB out
SCLK
VDD = 5.0 V
33879
Under
Test
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 5. Valid Data Delay Time
and Valid Time Test Circuit
SCLK
tR(DI)
0.7 VDD
< 50 ns tF(DI
50%
< 50 ns
3.3/5.0 V
0.2 VDD
0V
0.7 VDD
VOH
DO
0.2 VDD
(Low-to-High)
DO
(High-to-Low) 0.7 VDD
tR(DO
tVALID
VOL
VOH
0.2
VOL
Figure 6. Valid Data Delay Time
and Valid Time Waveforms
tF(CS)
tR(CS)
< 50 ns
CS
0.2 VDD
DO
(Tri-State to Low)
90%
10%
tDO(EN)
90%
< 50 ns
3.3/5.0 V
0.7 VDD
0V
tDO(DIS)
VTri-State
10% VOL
tDO(EN)
90%
tDO(DIS)
VOH
DO
(Tri-State to High)
10%
VTri-State
Figure 7. Enable and Disable Time Waveforms
33879
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
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