33879 Datasheet, PDF (11/24 Pages) Freescale Semiconductor, Inc – Configurable Octal Serial Switch with Open Load Detect Current Disable

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ V_DD ≤ 5.5 V, 5.5 V ≤ V_PWR ≤ 18 V, -40°C ≤ T_C ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with V_PWR = 13 V, T_A = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING ⁽¹⁴⁾
Recommended Frequency of SPI Operation ⁽¹⁴⁾
f _SPI
–
4.0
–
MHz
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t _LEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t _LAG
50
–
–
ns
DI to Falling Edge of SCLK (Required Setup Time)
t _{DI (SU)}
16
–
–
ns
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time ⁽¹⁵⁾
t _{DI (HOLD)}
20
–
–
ns
t _R(DI)
–
5.0
–
ns
DI, CS, SCLK Signal Fall Time ⁽¹⁵⁾
t _{F (DI)}
–
5.0
–
ns
Time from Falling Edge of CS to DO Low Impedance ⁽¹⁶⁾
t _{DO (EN)}
–
–
55
ns
Time from Rising Edge of CS to DO High Impedance ⁽¹⁷⁾
t _{DO (DIS)}
–
–
55
ns
Time from Rising Edge of SCLK to DO Data Valid ⁽¹⁸⁾
t _VALID
–
25
55
ns
Notes
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33879
11