56F8025_07 Datasheet, PDF (116/160 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Add.
Offset
Register Acronym
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
$0 GPIOD_PUPEN W
PU[15:0]
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R
$1
GPIOD_DATA W
D[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$2
GPIOD_DDIR W
DD[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$3 GPIOD_PEREN W
PE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
R
$4 GPIOD_IASSRT W
IA[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$5
GPIOD_IEN
W
IEN[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$6
GPIOD_IEPOL W
IEPOL[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
IPR[15:0]
$7
GPIOD_IPEND W
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$8
GPIOD_IEDGE W
IES[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
$9 GPIOD_PPOUTM W
OEN[15:0]
RS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R
RAW DATA[15:0]
$A GPIOD_RDATA W
RS 0 0 0 0 0 0 0 0 X X X X X X X X
R
$B
GPIOD_DRIVE W
DRIVE[15:0]
RS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 Read as 0
W
Reserved
RS
Reset
Figure 8-4 GPIOD Register Map Summary
56F8025 Data Sheet, Rev. 3
116
Freescale Semiconductor
Preliminary