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MC9S08DZ60_08 Datasheet, PDF (109/416 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU) | |||
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6.5.6.3 Port F Pull Enable Register (PTFPE)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTFPE7
0
6
PTFPE6
5
PTFPE5
4
PTFPE4
3
PTFPE3
2
PTFPE2
1
PTFPE1
0
0
0
0
0
0
Figure 6-39. Internal Pull Enable for Port F Register (PTFPE)
Table 6-37. PTFPE Register Field Descriptions
0
PTFPE0
0
Field
Description
7:0
PTFPE[7:0]
Internal Pull Enable for Port F Bits â Each of these control bits determines if the internal pull-up device is
enabled for the associated PTF pin. For port F pins that are conï¬gured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.6.4 Port F Slew Rate Enable Register (PTFSE)
R
W
Reset:
7
PTFSE7
0
6
PTFSE6
5
PTFSE5
4
PTFSE4
3
PTFSE3
2
PTFSE2
1
PTFSE1
0
0
0
0
0
0
Figure 6-40. Slew Rate Enable for Port F Register (PTFSE)
Table 6-38. PTFSE Register Field Descriptions
0
PTFSE0
0
Field
Description
7:0
PTFSE[7:0]
Output Slew Rate Enable for Port F Bits â Each of these control bits determines if the output slew rate control
is enabled for the associated PTF pin. For port F pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
109
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