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MC9S08DZ60_08 Datasheet, PDF (102/416 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU) | |||
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Chapter 6 Parallel Input/Output Control
6.5.4.3 Port D Pull Enable Register (PTDPE)
R
W
Reset:
7
PTDPE7
0
6
PTDPE6
5
PTDPE5
4
PTDPE4
3
PTDPE3
2
PTDPE2
1
PTDPE1
0
0
0
0
0
0
Figure 6-26. Internal Pull Enable for Port D Register (PTDPE)
Table 6-24. PTDPE Register Field Descriptions
0
PTDPE0
0
Field
Description
7:0
PTDPE[7:0]
Internal Pull Enable for Port D Bits â Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTD pin. For port D pins that are conï¬gured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port D bit n.
1 Internal pull-up/pull-down device enabled for port D bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.4.4 Port D Slew Rate Enable Register (PTDSE)
R
W
Reset:
7
PTDSE7
0
6
PTDSE6
5
PTDSE5
4
PTDSE4
3
PTDSE3
2
PTDSE2
1
PTDSE1
0
0
0
0
0
0
Figure 6-27. Slew Rate Enable for Port D Register (PTDSE)
Table 6-25. PTDSE Register Field Descriptions
0
PTDSE0
0
Field
Description
7:0
PTDSE[7:0]
Output Slew Rate Enable for Port D Bits â Each of these control bits determines if the output slew rate control
is enabled for the associated PTD pin. For port D pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ60 Series Data Sheet, Rev. 4
102
Freescale Semiconductor
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