F71872 Datasheet, PDF (80/115 Pages) Feature Integration Technology Inc. – Super H/W Monitor + LPC IO

F71872
4 ^FAN1_DC_MODE
3 _{F1_LATCH_FULL}
2 _{F1_KEEP_STOP}
1-0 _{F1_MODE}
R/W 0 ^{Set to 1, FAN1 control is set to DC mode.}
Set to 0, FAN1 control is set to PWM duty-cycle mode.
R/W 0 ^{Set to 1, current FAN1 COUNT will be bypass to FAN1_FULL_SPEED.}
R/W 0 ^{Set to 1, keep FANPWM1 duty-cycle decrease to STOP DUTY and hold.}
R/W 00 ^{00: FAN1 operates in SPEED mode. FANPWM duty-cycle is automatically}
adjusted according to FAN EXPECT register.
01: FAN1 operates in TEMPERATURE mode. FANPWM duty-cycle is
automatically adjusted according to current temperature,
1x: FAN1 operates in MANUAL mode. Software set the FANPWM duty-cycle
directly.
7.6.3.29 FANPWM1 START UP DUTY-CYCLE  Index 61h
Bit
Name
R/W Default
Description
7-0 F1_START_DUTY[9:2] R/W 30h FANPWM1 will increasing duty-cycle from 0 to this valuedirectly.
7.6.3.30 FANPWM1 STOP DUTY-CYCLE  Index 62h
Bit
Name
7-0 F1_STOP_DUTY[9:2]
R/W Default
Description
R/W 25h FANPWM1 will decreasing duty-cycle to 0 from this value directly or keep
duty-cycle in this value when FAN1_KEEP_STOP set to 1.
7.6.3.31 FANPWM1 Output Frequency Control  Index 63h
Bit
Name
R/W Default
Description
7 PWM1_DIV[7]
6-0 PWM1_DIV[6:0]
R/W 80h Set to 1, PRECLK(Pre-Clock) = 48M Hz ;
Set to 0, PRECLK
= 1M Hz .
R/W
Pre-divisor of PRECLK.
PRECLK
FANPWM1 output frequency =
(Pr e - divisor) ∗ 256
So, PWM frequency ranges from 30.5Hz~187.5KHz
7.6.3.32 FANPWM1 STEP Control Register -- Index 64h
Bit
Name
7-4
F1_UP_STEP
3-0 F1_DOWN_STEP
R/W Default
Description
R/W 00h This value determines the increasing speed of PWM1_DUTY.
R/W
This value determines the decreasing speed of PWM1_DUTY.
7.6.3.33 FAN1_FAULT TIME Register  Index 65h
Bit
Name
R/W Default
Description
78
July, 2007
V0.28P