F71872 Datasheet, PDF (79/115 Pages) Feature Integration Technology Inc. – Super H/W Monitor + LPC IO

F71872
3 EN_VIN3_BEEP
2 EN_VIN2_BEEP
1 EN_VIN1_BEEP
0 EN_VCC_BEEP
R/W 0 Write 1 to enable the beep alarm for VIN3 abnormal event. Write 0 to disable it.
R/W 0 Write 1 to enable the beep alarm for VIN2 abnormal event. Write 0 to disable it.
R/W 0 Write 1 to enable the beep alarm for VIN1 abnormal event. Write 0 to disable it.
R/W 0 Write 1 to enable the beep alarm for 3VDD abnormal event. Write 0 to disable
it.
7.6.3.26 BEEP Control Register 2  Index 3Eh
Bit
Name
R/W Default
Description
7-6 Reserved
-
-
5 EN_T3_BEEP
4 EN_T2_BEEP
3 EN_T1_BEEP
2 EN_VBAT_BEEP
1 EN_VIN7_BEEP
0 EN_VIN8_BEEP
R/W 0 Write 1 to enable the beep alarm for T3 abnormal event. Write 0 to disable it
R/W 0 Write 1 to enable the beep alarm for T2 abnormal event. Write 0 to disable it
R/W 0 Write 1 to enable the beep alarm for T1 abnormal event. Write 0 to disable it
R/W 0 Write 1 to enable the beep alarm for VBAT abnormal event. Write 0 to disable
it
R/W 0 Write 1 to enable the beep alarm for VSB abnormal event. Write 0 to disable it
R/W 0 Write 1 to enable the beep alarm for VIN8 abnormal event. Write 0 to disable it
7.6.3.27 BEEP Control Register 3  Index 3Fh
Bit
Name
R/W Default
Description
7 Reserved
-
6 EN_CASE_BEEP R/W
5 EN_FAN3_TAR_
R/W
BEEP
4 EN_FAN2_TAR_
R/W
BEEP
3 EN_FAN1_TAR_BEE R/W
P
2 EN_FAN3_LMT_BEE R/W
P
1 EN_FAN2_LMT_BEE R/W
P
0 EN_FAN1_LMT_BEE R/W
P
-
0 Write 1 to enable the beep alarm for CASEOPEN abnormal event. Write 0 to
disable it
0 Write 1 to enable the beep alarm for FAN3 target-not-reached event. Write 0 to
disable it
0 Write 1 to enable the beep alarm for FAN2 target-not-reached event. Write 0 to
disable it
0 Write 1 to enable the beep alarm for FAN1 target-not-reached event. Write 0 to
disable it
0 Write 1 to enable the beep alarm for FAN3 under-limit event. Write 0 to disable
it
0 Write 1 to enable the beep alarm for FAN2 under-limit event. Write 0 to disable
it
0 Write 1 to enable the beep alarm for FAN1 under-limit event. Write 0 to disable
it
7.6.3.28 FAN1 OPERATING Control Register -- Index 60h
Bit
Name
R/W Default
Description
7 FAN1_SKIP
R
6 Reserved
-
5 ^{FAN1_FORCE_MONI} R/W
TOR
- When this bit is set to 1, FAN1 is not monitored.
When this bit is set to 0, FAN1 is monitored.
-
0 ^{Set to 1, FAN1 speed is monitored every monitor cycle even the fan is}
stopped. Set to 0, FAN1 speed will not be monitored at the next monitor cycle
if the fan is stopped.
77
July, 2007
V0.28P