F71872 Datasheet, PDF (64/115 Pages) Feature Integration Technology Inc. – Super H/W Monitor + LPC IO

F71872
7.5 Parallel Port Registers
7.5.1 Logic Device Number Register
Logic Device Number Register  Index 07H
Bit
Name
R/W Default
Description
7-0 LDN
R/W 00h 00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select VID device configuration registers.
0ah: Select PME & ACPI device configuration registers.
7.5.2 Parallel Port Configuration Register
Parallel Port Device Enable Register  Index 30h
Bit
Name
R/W Default
7-1 Reserved
0 PRT_EN
-
- Reserved
R/W 1 0: disable Parallel Port.
1: enable Parallel Port.
Description
Base Address High Register  Index 60h
Bit
Name
R/W Default
Description
7-0 BASE_ADDR_HI
R/W 03h The MSB of Parallel Port base address.
Base Address Low Register  Index 61h
Bit
Name
R/W Default
Description
7-0 BASE_ADDR_LO R/W 78h The LSB of Parallel Port base address.
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July, 2007
V0.28P