MC81F4204 Datasheet, PDF (73/150 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4204
11. INTERRUTP CONTROLLER
External Interrupt 1
External Interrupt 3
External Interrupt 5
External Interrupt 6
External Interrupt 0
External Interrupt 2
External Interrupt 4
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
Timer0 matchInterrupt
Timer0 overflow Interrupt
Timer1 matchInterrupt
Timer1 overflow Interrupt
Timer2 matchInterrupt
Timer2 overflow Interrupt
SIO Interrupt
Watchdog Timer Interrupt
Basic Timer Interrupt
Interrupt
Request
EXT1IR
EXT3IR
EXT5IR
EXT6IR
EXT0IR
EXT2IR
EXT4IR
EXT7IR
EXT8IR
EXT9IR
EXT10IR
EXT11IR
T0MIR
T0OVIR
T1MIR
T1OVIR
T2MIR
T2OVIR
SIOIR
WDTIR
BTIR
Interrupt
Enable
EXT1IE
EXT3IE
EXT5IE
EXT6IE
EXT0IE
EXT2IE
EXT4IE
EXT7IE
EXT8IE
EXT9IE
EXT10IE
EXT11IE
T0MIE
T0OVIE
T1MIE
T1OVIE
T2MIE
T2OVIF
SIOIE
WDTIE
BTIE
Interrupt
EINTF
Flag
INTFH ^Interrupt
Flag
Release STOP/SLEEP
To CPU
I-flag
Interrupt
Master
Enable
Flag
Interrupt
Vector
Address
Generator
Figure 11-1 Block Diagram of Interrupt
The MC81F4204 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request
flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). And 21 interrupt
sources are provided.
The interrupt vector addresses are shown in „11.6 Interrupt Vector & Priority Table‟ on page 81.
Interrupt enable registers are shown in next paragraph. These registers are composed of interrupt
enable flags of each interrupt source and these flags determine whether an interrupt will be accepted
or not. When the enable flag is “0”, a corresponding interrupt source is disabled.
Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
October 19, 2009 Ver.1.35
73