MC81F4204 Datasheet, PDF (124/150 Pages) Finechips – ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC81F4204
23.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripheral clock is stopped. With the clock
frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins
out the values held by their respective port data register, port direction registers. Oscillator stops and
the systems internal operations are all held up.
The states of the RAM, registers, and latches valid immediately before the system is put in the STOP
state are all held.
The program counter stop the address of the instruction to be executed after the instruction "STOP"
which starts the STOP operating mode.
Note :
The Stop mode is activated by execution of STOP instruction after setting the SSCR to
“5AH”. (This register should be written by byte operation. If this register is set by bit
manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired
operation)
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be
taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is
restored to its normal operating level, before the Stop mode is terminated.
The reset should not be activated before VDD is restored to its normal operating level, and must be
held active long enough to allow the oscillator to restart and stabilize.
Note :
After STOP instruction, at least two or more NOP instruction should be written.
Ex)
LDM CKCTLR,#0FH
;more than 20ms
LDM SSCR,#5AH
STOP
NOP
;for stabilization time
NOP
;for stabilization time
In the STOP operation, the dissipation of the power associated with the oscillator and the internal
hardware is lowered; however, the power dissipation associated with the pin interface (depending
on the external circuitry and program) is not directly determined by the hardware operation of the
STOP feature. This point should be little current flows when the input level is stable at the power
voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by
approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an
I/O port puts the pin signal into the high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other means.
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October 19, 2009 Ver.1.35