CMP0817BA0-I Datasheet, PDF (7/10 Pages) FIDELIX – 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP0817BA0-I
READ CYCLE (1) (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
CMOS LPRAM
Data Valid
READ CYCLE (2) (CS2=/WE=VIH)
Address
/CS1
tRC
tAA
tOH
tCO
CS2
/UB, /LB
/OE
Data Out
High-Z
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tHZ
tBHZ
tOHZ
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
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Revision 0.3
Sep. 2006