CMP0817BA0-I Datasheet, PDF (5/10 Pages) FIDELIX – 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

CMP0817BA0-I
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
CMOS LPRAM
30pf
1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C)
Parameter List
Symbol
70ns
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Min
Max
tRC
70
80k
tAA
-
70
tCO
-
70
tOE
-
25
/UB, /LB Access Time
tBA
-
70
Read
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
tLZ
10
-
tBLZ
10
-
Output Enable to Low-Z Output
tOLZ
5
-
Chip Disable to High- Z Output
tHZ
0
5
/UB, /LB Disable to High- Z Output
tBHZ
0
5
Output Disable to High- Z Output
tOHZ
0
5
Output Hold from Address Change
tOH
5
-
Write Cycle Time
tWC
70
80k
Chip Select to End of Write
tCW
60
-
Address Set-up Time
tAS
0
-
Address Valid to End of Write
tAW
60
-
Write
/UB, /LB Valid to End of Write
Write Pulse Width
tBW
60
-
tWP
50
-
Write Recovery Time
tWR
0
-
Write to Output High-Z
tWHZ
0
5
Data to Write Time Overlap
tDW
20
-
Data Hold from Write Time
End Write to Output Low-Z
/CS High Pulse Width¹⁾
tDH
0
-
tOW
5
-
tCP
10
-
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
Revision 0.3
Sep. 2006