FXL2SD106_11 Datasheet, PDF (9/11 Pages) Fairchild Semiconductor – Low-Voltage Dual-Supply 6-Bit Voltage Translator with Auto-Direction Sensing

DATA
IN
t_pxx
DATA
OUT
V_mi
t_pxx
V_CCI
GND
V_CCO
V_mo
Input t_R = t_F = 2.0ns, 10% to 90%
Input t_R = t_F = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 2. Waveform for Inverting and
Non-inverting Functions
OUTPUT
CONTROL
V_mi
t_PZL
DATA
OUT
V_Y
V_CCA
GND
V_OL
Input t_R = t_F = 2.0ns, 10% to 90%
Input t_R = t_F = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 3. 3-STATE Output Low Enable Time for Low
Voltage Logic
OUTPUT
CONTROL
V_mi
t_PZH
DATA
V_x
OUT
V_CCA
GND
V_OH
Input t_R = t_F = 2.0ns, 10% to 90%
Input t_R = t_F = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 4. 3-STATE Output High Enable Time for
Low Voltage Logic
Symbol
Vmi⁽¹⁵⁾
Vmo
VX
VY
Vcc
V_CCI / 2
V_CCO / 2
0.9 x V_CCO
0.1 x V_CCO
Note:
15. V_CCI = V_CCA for control pin OE or Vmi = (V_CCA / 2).
VOUT
t_rise
V_OH
80% x V_CCO
20% x V_CCO
V_OL
Time
I_OHD ≈ (C_{L +}C_I/O) x
ΔV_OUT
Δt
=
(C_L
+^CI/O⁾
x
(20%
–
80%)
t_RISE
x
V_CCO
Figure 5. Active Output Rise Time and Dynamic
Output Current High
V_OH
t_fall
VOUT
80% x V_CCO
20% x V_CCO
V_OL
Time
I_OLD ≈ (C_{L +}C_I/O) x
ΔV_OUT
Δt
=
(80%
(C_{L +}C_I/O) x
– 20%) x V_CCO
t_FALL
Figure 6. Active Output Fall Time and Dynamic
Output Current Low
t_W
DATA
IN
V_CCI/2
V_CCI/2
Max. data rate, f = 1/t_W
Figure 7. Maximum Data Rate
V_CCI
GND
DATA
OUTPUT
V_mo
t_skew
V_mo
V_CCO
GND
t_skew
DATA
OUTPUT
V_mo
V_CCO
V_mo
GND
t_skew = (t_pHLmax – t_pHLmin) _or (t_pLHmax – t_pLHmin)
Figure 8. Output Skew Time
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
9
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