FXL2SD106_11 Datasheet, PDF (2/11 Pages) Fairchild Semiconductor – Low-Voltage Dual-Supply 6-Bit Voltage Translator with Auto-Direction Sensing

Connection Diagram
VCCA VCCB
1
16
CLK IN 2
15 _{CLK OUT}
A₀
3
14
B₀
A₁
4
13
B₁
A₂
5
12
B₂
A₃
6
11
B₃
A₄
7
10
B₄
8
9
OE GND
Pin Description
Number Name
Description
1
V_CCA A-Side Power Supply
2
CLK IN A-Side Input
3–7
A₀–A₄ A-Side Inputs or 3-State Outputs
8
OE Output Enable Input
9
GND Ground
10–14 B₄–B₀ B-Side Inputs or 3-State Outputs
15 CLK OUT 3-State Output
16
V_CCB B-Side Power Supply
Functional Diagram
VCCA
VCCB
OE
A0 – A4
B0 – B4
CLK IN
CLK OUT
Function Table
Control
OE
LOw Logic Level
HIGH Logic Level
Outputs
3-State
Normal Operation
Power-Up/Power-Down Sequencing
FXL translators offer an advantage in that either V_CC
may be powered up first. This benefit derives from the
chip design. When either V_CC is at 0 volts, outputs are in
a high-impedance state. The control input (OE) is
designed to track the V_CCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus con-
tention, excessive currents, or oscillations do not occur
during power-up / power-down. The size of the pull-down
resistor is based upon the current-sinking capability of
the device driving the OE pin.
The recommended power-up sequence is the following:
1. Apply power to the first V_CC.
2. Apply power to the second V_CC.
3. Drive the OE input high to enable the device.
The recommended power-down sequence is the
following:
1. Drive OE input low to disable the device.
2. Remove power from either V_CC.
3. Remove power from other V_CC.
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
2
www.fairchildsemi.com