FMS6403_08 Datasheet, PDF (9/14 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD Bypass Filters for RGB and YPbPr Signals

Functional Description
Introduction
The FMS6403 is a next-generation filter solution from
Fairchild Semiconductor addressing the expanding
filtering needs for televisions, set-top boxes, and DVD
players, including progressive scan capability. The
product provides selectable filtering with cutoff
frequencies of 30MHz, 15MHz, and 8MHz for all three
channels. In addition, the filters can be bypassed for
wider bandwidth applications. The FMS6403 allows
consumer devices to support a variety of resolution
standards with the same hardware.
Multiplexers on the channel inputs are controlled by the
IN2_SEL pin. The RGB_SEL pin can be used to set the
sync tip clamp voltages for YPbPr or RGB applications.
All three channels are set for 250mV sync tips to reduce
DC-coupled power dissipation for RGB inputs. The
lower output bias voltage is not suitable for the PbPr
outputs; so for YPbPr inputs, these signals are clamped
to 1.125V, while Y is still clamped to 250mV. Sync tip
clamping voltages are set by forcing the desired DC
bias level during the active sync period. For systems
without sync on Y/G, an external sync input is provided.
If sync exists on one input Y/G signal, but not on the
other Y/G input signal, the IN2_SEL and EXT_SYNC
control inputs may be wired together on the PCB to
switch the sync source with the input source. Both
standard-definition (bi-level) and high-definition (tri-
level) sync are supported at the Y/G inputs and
SYNC_IN depending on the FSEL[1:0] inputs. See the
Sync Processing section for further details.
Standard-definition (480i) and progressive (480p)
signals are clamped by forcing the signal to the desired
voltage during the sync pulse. For signals with sync, the
sync tip itself is forced to the clamp voltage (typically
250mV). When high-definition (HD) sync is present (tri-
level sync) the sync tip duration is too short to allow this
approach. To accurately clamp HD signals, the sync
pulse starts a timer and the actual clamping is done at
the blanking level right after the sync pulse. The sync tip
is typically placed at 250mV if its amplitude is 300mV.
All three outputs are driven by amplifiers with selectable
gains of 0dB or +6dB. The gain is set with the 0dB_SEL
pin. These amplifiers can drive two terminated video
loads (75Ω) to 2VPP with a 1VPP input when set to 6dB
gain. The input range is limited to 1.5VPP and the output
range is limited to 2.5VPP.
All control inputs must be driven high or low. Do not
leave them floating.
External SYNC Mode
The FMS6403 can properly recover sync timing from
video signals that include sync. If the Y-input video
signals do not include sync, the FMS6403 can be used
in sxternal SYNC mode. In external sync mode,
(EXT_SYNC pin is high), a pulsed input must be applied
to the SYNC_IN pin. If there is no video signal present,
therefore no sync signal present, there must be an input
applied to the SYNC_IN pin. When there is no video
signal on the video inputs, SYNC_IN can be a sync
pulse every 60μs to mimic the slowest sync in a regular
video signal. The following two sections discuss the
sync processing and timing required in more detail.
SD and Progressive Scan Video Sync
Processing
The FMS6403 must control the DC offset of AC-coupled
input signals since the average DC level of video varies
with image content. If the input offset is allowed to
wander, the common-mode input range of the amplifiers
can be exceeded, leading to signal distortion. DC offset
adjustment is referred to as “clamping” or, in some
cases, biasing, and must be done at the correct time
during each video line. The optimum time is during the
sync pulse, since it is the lowest input voltage. This
approach works well for 480i and 480p signals since the
sync tip duration is long enough to allow the DC-offset
errors to be compensated from line to line. The DC-
offset of the sync tip is adjusted as illustrated in Figure
15 by forcing a current on the input during the sync
pulse. The sync tip is clamped to approximately 250mV.
Signals like Pb and Pr with a symmetric voltage range
(±350mV) are clamped to approximately 1.125V. Note
that the following diagrams illustrate DC restore
functionality and indicate output voltage levels for both
0dB and 6dB gain (1VPP and 2VPP video signals at the
output pin).
Figure 15. Bi-level Sync Tip Clamping and Bias
In some cases, the sync voltage may be compressed to
less than the nominal 300mV value. The FMS6403 can
successfully recover SD and progressive scan sync
greater than 100mV (compressed to 33% of nominal).
The FMS6403 can properly recover sync timing from
luma and green, which include sync. If none of the
video signals includes sync, the EXT_SYNC control
input can be set high and an external sync signal must
be input on the SYNC_IN pin. Refer to the External
Sync section for more details. The timing required for
this operating mode is shown in Figure 16. SYNC
timings, T1 and T2, are defined in the SD Electrical
Specifications section.
© 2005 Fairchild Semiconductor Corporation
FMS6403 • Rev. 1.0.4
9
www.fairchildsemi.com