FMS6403_08 Datasheet, PDF (3/14 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/PS/SD Bypass Filters for RGB and YPbPr Signals

Pin Configuration
Pin Definitions
Figure 3. Pin Configuration
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
EXT_SYNC
RGB_SEL
Y1/G1
Y2/G2
Pb1/B1
Pb2/B2
Pr1/R1
Pr2/R2
FSEL0
FSEL1
GND
GND
0dB_SEL
Pr/ROUT
Pb/BOUT
Y/GOUT
In2_SEL
SYNC_IN
VCC
VCC
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Description
Selects the external SYNC_IN signal when set to logic 1; do not float.
Selects RGB clamp levels when set to logic 1. YPbPr clamps levels when set to
logic 0; do not float.
Y or G input 1 - may be connected to a signal that includes sync.
Y or G input 2 - may be connected to a signal that includes sync.
Pb or B input 1.
Pb or B input 2.
Pr or R input 1.
Pr or R input 2.
Selects filter corner frequency or bypass, see Table 2. Do not float.
Selects filter corner frequency or bypass, see Table 2. Do not float.
Must be tied to ground, do not float.
Must be tired to ground, do not float.
Selects output gain of 0dB when set to logic 1; 6dB when set to logic 0. Do not
float.
Pr or R output.
Pb or B output.
Y or G output.
Selects MUX input 2 when set to logic 1; MUX input 1 when set to logic 0. Do not
float.
External sync inputs signal, square wave crossing VIL and VIN input thresholds. Do
not float.
+5V supply. Do not float.
+5V supply. Do not float.
© 2005 Fairchild Semiconductor Corporation
FMS6403 • Rev. 1.0.4
3
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